Glass-Substrate Leadless Package for Galvanic Isolation
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Solution Overview
Problem
Conventional isolation methods for semiconductor circuits face limitations such as bulkiness, limited bandwidth, susceptibility to environmental factors, and challenges in leadless package designs, including electrostatic discharge risks and complex manufacturing processes.
Innovation Solution
A leadless package using a glass substrate with integrated inductive coupling between semiconductor dies, eliminating the need for external components and coatings, and ensuring galvanic isolation through electrically conductive top and bottom plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional isolation components (optocouplers, capacitors, transformers) are used, then galvanic isolation is achieved, but the device becomes bulky and has limited bandwidth
Solution Approach 1:
The patent merges the isolation function with the semiconductor die structure itself by integrating an inductive isolator directly into the leadless package. The inductive isolator comprises first and second inductive elements with different magnetic coupling coefficients, where the first inductive element couples to a first circuit and the second inductive element couples to a second circuit at a different voltage level. This integration eliminates the need for separate external isolation components, achieving both compact size and effective galvanic isolation.
2Volume of moving object
If integrated isolators are used to reduce size, then device compactness is improved, but insulation distance is limited leading to ESD risks
Solution Approach 1:
The patent transitions from planar isolation to three-dimensional isolation by positioning the inductive isolator between the semiconductor die and the leadless package substrate. The inductive elements are arranged with specific spatial relationships - the first inductive element is positioned above the leadless package substrate while the second inductive element is positioned on the semiconductor die, creating vertical separation that enhances insulation distance and ESD protection while maintaining compact footprint.
3Area of stationary object
If leadless package configuration is used, then footprint is reduced, but manufacturing complexity increases due to lead frame split
Solution Approach 1:
The patent extracts the complex lead frame structure from the package design and replaces it with a simplified substrate-based interconnection approach. The inductive isolator is integrated directly into the leadless package substrate, eliminating the need for lead frame splits and associated manufacturing complexities. This extraction of the lead frame function allows for simpler manufacturing processes while maintaining the compact footprint benefits of leadless packaging.
4Reliability
If conventional isolation methods are used, then voltage level isolation is achieved, but bandwidth is limited
Solution Approach 1:
The patent utilizes parameter changes in the magnetic coupling coefficients of the inductive elements to optimize both isolation and bandwidth performance. The first inductive element has a first magnetic coupling coefficient when coupled to the second inductive element, and a second magnetic coupling coefficient when coupled to a third inductive element. By controlling and varying these magnetic coupling coefficients, the patent achieves effective voltage level isolation while maintaining wide bandwidth capability, overcoming the limitations of conventional isolation methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides compact, reliable, and environmentally shielded semiconductor devices with enhanced insulation and simplified manufacturing, suitable for demanding environments.
Implementation Method 1
an inductive coupling is provided between: said first electrically conductive plate and said inductive plate, and said second electrically conductive plate and said inductive plate
Data Source
Figure 1a~1b
Figure 2a~2c
Figure 2d
AI summary
A leadless package, comprising: a glass substrate; first and second electrically conductive interconnect route layers provided on a top side of said glass substrate, wherein the first and second electrically conductive interconnect route layers are isolated from each other; first and second electrically conductive top plates provided on said top side of said glass substrate; a first semiconductor die having at least two terminals, wherein a first of said two terminals is connected to the first electrically conductive interconnect route layer and a second of said at least two terminals is connected to said first electrically conductive top plate; a second semiconductor die having at least two terminals, wherein a first of said two terminals is connected to the second electrically conductive interconnect route layer and a second of said at least two terminals is connected to said second electrically conductive top plate; a first via through said glass substrate for enabling an electrical connection from a bottom side of said glass substrate to said first electrically conductive plate; a second via through said glass substrate for enabling an electrical connection from said bottom side of said glass substrate to said second electrically conductive plate; an inductive plate provided in or at said top side of said glass substrate, wherein said inductive plate is oriented such that an inductive coupling is provided between: said first electrically conductive plate and said inductive plate, and said second electrically conductive plate and said inductive plate.