Glass Package Substrate Stacks With Embedded Interconnect Bridges
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Solution Overview
Problem
Glass core substrates in integrated circuit packages are prone to seware failures due to defects and thermal expansion mismatches, leading to cracks and reduced reliability.
Innovation Solution
Implementing a substrate core with multiple discrete glass layers having different coefficients of thermal expansion (CTEs) to create a graded thermal expansion profile, reducing stress and embedding an interconnect bridge within the glass core to eliminate the need for a thick build-up region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single glass core substrate is used, then the substrate provides structural support and electrical interconnects, but it is prone to seware failures due to thermal expansion mismatches and defects
Solution Approach 1:
The patent divides the single glass core substrate into multiple discrete glass layers (first glass layer, second glass layer, third glass layer) with different coefficients of thermal expansion. This segmentation allows each layer to accommodate thermal expansion differently, reducing stress concentration and preventing seware failures that occur in monolithic glass substrates.
Solution Approach 2:
The patent creates a composite glass layer structure where layers with different thermal expansion properties are bonded together. The first glass layer has a first coefficient of thermal expansion, the second glass layer has a second coefficient of thermal expansion, and the third glass layer has a third coefficient of thermal expansion. This composite structure provides both mechanical support and thermal management, enhancing overall substrate reliability.
2Reliability
If multiple glass layers with different CTEs are implemented, then thermal expansion gradients are smoothed and reliability is enhanced, but the manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by assigning different coefficients of thermal expansion to specific glass layers at different positions within the substrate. The first glass layer (closest to the die), second glass layer (intermediate), and third glass layer (farthest from the die) each have tailored CTE values. This local differentiation optimizes thermal management at each interface while maintaining overall structural integrity, enhancing reliability without requiring complete redesign of the entire substrate.
3Reliability
If a thick build-up region is used to accommodate interconnects, then electrical interconnects can be established, but the package substrate thickness increases and signal transmission performance deteriorates
Solution Approach 1:
The patent embeds the interconnect bridge structure within the glass layers themselves rather than requiring a separate thick build-up region. The interconnect bridge is nested between the first glass layer and the second glass layer, with conductive vias passing through the glass layers to establish electrical connections. This nesting approach integrates the interconnect function into the structural glass layers, eliminating the need for additional thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes seware failures, enhances the reliability and yield of IC packages by smoothing thermal expansion gradients and providing die-to-die interconnects without additional build-up regions.
Implementation Method 1
glass layers having different coefficients of thermal expansion (CTEs) to create a graded thermal expansion profile, reducing stress
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods for package substrates with stacks of glass layers including interconnect bridges are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a cavity defined therein; a second glass layer different from the first glass layer; and an interconnect bridge at least partially in the cavity. The interconnect bridge electrically couples a first semiconductor die to a second semiconductor die.