Glass Package Substrate Stack for Thermal Stress and Power Delivery
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Solution Overview
Problem
Glass core substrates in integrated circuit packages are prone to seware failures due to defects and thermal expansion mismatches, leading to cracks and mechanical instability, which affect signal transmission and power delivery.
Innovation Solution
Implementing multiple distinct glass cores with varying coefficients of thermal expansion (CTE) stacked together, along with a buffer material to absorb stress, and using power delivery interconnects like coaxial magnetic inductor loops and plated magnetic vias to enhance electrical pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If multiple glass layers with different CTEs are stacked to reduce thermal stress, then mechanical stability is improved, but the device complexity increases
Solution Approach 1:
The patent uses a composite structure of multiple glass layers with different CTEs, bonded together to create a gradient substrate. This composite approach provides thermal stress resistance while maintaining a relatively simple overall structure that can be manufactured using standard PCB fabrication processes.
2Power
If power delivery interconnects are implemented through glass layers, then power delivery capability is improved, but the manufacturing precision requirements increase due to drilling and plating through glass
Solution Approach 1:
The patent performs preliminary drilling of holes through the glass layers before stacking and bonding the glass layers together. This preliminary action allows for easier drilling in the individual, softer glass layers compared to drilling through the complete stacked structure, thereby reducing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of seware failures by minimizing stress through CTE gradation and provides improved mechanical support and signal integrity, while also facilitating efficient power delivery within the package substrate.
Implementation Method 1
a buffer material to absorb stress
Implementation Method 2
glass layers having different coefficients of thermal expansion
Implementation Method 3
power delivery interconnects like coaxial magnetic inductor loops and plated magnetic vias to enhance electrical pathways
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.