Glass Via Bar for Semiconductor Package Height Reduction
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Solution Overview
Problem
Current semiconductor device packages face challenges such as increased height, large footprint, limited flexibility in sourcing memory dies, high cost of interposers, and inefficient thermal management due to vertical stacking and the use of expensive TSV technology.
Innovation Solution
The use of glass via bars with through-glass vias (TGVs) and embedded passive components, which allow for flexible design options, reduced package height and footprint, and improved thermal management by enabling side-by-side placement of logic and memory dies, while eliminating the need for expensive redistribution layers and reducing interconnection lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If vertical stacking of packages is used to integrate logic and memory dies, then interconnection length is reduced, but package height increases
Solution Approach 1:
The patent transitions from vertical stacking (3D PoP) to lateral/planar arrangement (2.5D) using an interposer substrate. Logic die and memory dies are arranged side-by-side on the interposer rather than stacked vertically, reducing package height while maintaining short interconnection paths through the interposer's conductive vias and traces.
2Adaptability or versatility
If TSV technology is used for interconnection, then vertical integration is enabled, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive TSV technology with a cost-effective interposer substrate approach using standard through-substrate vias and conductive traces. The interposer acts as a disposable intermediate structure that enables vertical integration functionality without the high manufacturing costs of TSV, using more economical fabrication processes.
3Adaptability or versatility
If logic and memory dies are packaged separately in PoP, then testability and flexibility are improved, but package footprint increases
Solution Approach 1:
The patent merges separate logic and memory die packages into a unified 2.5D package structure using an interposer substrate. Both die types are integrated on the same substrate plane, reducing overall package footprint while maintaining separate testability and flexibility through the interposer's independent connection paths and modular architecture.
4Productivity
If wide I/O interfaces are supported, then memory bandwidth is increased, but package complexity increases
Solution Approach 1:
The interposer substrate serves multiple functions simultaneously: it provides mechanical support, electrical interconnection, thermal management pathways, and signal routing for wide I/O interfaces. This multi-functionality enables high memory bandwidth through wide interfaces without proportionally increasing package complexity, as the interposer handles multiple roles in a single component.
Data Source
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AI summary
A semiconductor device comprising a second surface of a logic die and a second surface of a via bar coupled to a first surface of a substrate, a second surface of a memory die coupled to a first surface of the via bar, a portion of the second surface of the memory die extending over the first surface of the logic die, such that the logic die and the memory die are vertically staggered, and the memory die electrically coupled to the logic die through the via bar. The via bar can be formed from glass, and include through-glass vias (TGVs) and embedded passives such as resistors, capacitors, and inductors. The semiconductor device can be formed as a single package or a package-on-package structure with the via bar and the memory die encapsulated in a package and the substrate and logic die in another package.