Glass Via Semiconductor Structure for Dense RDL Interconnects
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Solution Overview
Problem
Existing circuit boards for semiconductor components are not entirely satisfactory in terms of integration density and electrical connectivity, limiting the potential for further miniaturization and performance enhancement.
Innovation Solution
A method involving the formation of deep vias and redistribution layers on a glass or quartz carrier, using electroplating processes to create fine-line patterns, and integrating semiconductor dies directly onto a glass substrate, which includes embedded passive devices, to enhance electrical connectivity and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional circuit boards are used for semiconductor components, then existing manufacturing processes can be maintained, but integration density and electrical connectivity are limited
Solution Approach 1:
The patent changes the fundamental material parameter of the substrate from conventional PCB materials to glass or quartz, enabling higher integration density and improved electrical performance. This material parameter change allows for finer feature sizes and better signal integrity while maintaining manufacturability through adapted processes.
Solution Approach 2:
The invention segments the circuit board structure into distinct functional layers including substrate, conductor patterns, and solder resist layers, allowing each layer to be optimized independently for its specific function while achieving overall high integration density.
2Manufacturing precision
If feature size is reduced to increase integration density, then more components can be integrated, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary actions by pre-forming the glass or quartz substrate with appropriate properties before circuit patterning, and by using pre-designed conductor patterns that facilitate subsequent manufacturing steps. This preliminary preparation enables reduced feature sizes while keeping the overall manufacturing process manageable.
3Loss of energy
If conventional substrates are used, then existing processes can be maintained, but power loss and thermal management are insufficient
Solution Approach 1:
The patent employs composite material structures combining glass or quartz substrate with metal conductor layers and solder resist coatings. This composite approach reduces power loss through the inherent electrical properties of glass/quartz while the layered structure provides integrated thermal management capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables high electrical performance with low power loss and adjustable coefficient of thermal expansion, allowing for smaller, more integrated semiconductor structures with simplified manufacturing processes.
Implementation Method 1
using electroplating processes to create fine-line patterns
Data Source
AI summary
A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.