G-LDPC Bit-Flipping Decoder with Dual Syndrome Tables

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Solution Overview

Problem

Existing G-LDPC decoding systems are inefficient due to high latency, power consumption, and processing cycles, as they are designed for worst-case error correction, which is not necessary for most error scenarios, leading to a need for a low-complexity decoding scheme that can handle most errors quickly without excessive hardware complexity.

Innovation Solution

Implementing a dual-decoder system that uses a faster, less complex decoder for routine error correction and switches to a slower, more complex decoder only when necessary, utilizing two syndrome tables (S-table and L-table) for bit-flipping operations to update reliabilities and correct errors efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a G-LDPC decoder is designed to correct for the worst case correction capability, then error correction reliability is improved, but decoding speed and hardware complexity deteriorate

Engineering Contradiction:

Improveerror correction capabilityVSAvoiddecoding speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The decoding system is segmented into two distinct decoders: a first decoder optimized for fast decoding of typical error patterns, and a second decoder optimized for correcting worst-case error scenarios. This segmentation allows the system to achieve high speed for common cases while maintaining high reliability for rare worst-case scenarios, resolving the contradiction between speed and reliability.

Inventive Principle:

Principle #1Segmentation

2Reliability

If a G-LDPC decoder is designed to correct for the worst case correction capability, then error correction reliability is improved, but hardware complexity deteriorates

Engineering Contradiction:

Improveerror correction capabilityVSAvoidhardware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

3Reliability

If a G-LDPC decoder is designed to correct for the worst case correction capability, then error correction reliability is improved, but power consumption deteriorates

Engineering Contradiction:

Improveerror correction capabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

4Reliability

If a G-LDPC decoder is designed to correct for the worst case correction capability, then error correction reliability is improved, but processing cycles deteriorate

Engineering Contradiction:

Improveerror correction capabilityVSAvoidprocessing cycles

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10707899B2Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes

Publication Date: 2020.07.07 SK HYNIX INC

AI summary

Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.