GLDPC Decoder Architecture for Low-Complexity Error Correction

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Solution Overview

Problem

The complexity of decoding Generalized Low Density Parity-Check (GLDPC) codes is prohibitively high, hindering their practical implementation despite their potential for improved error resilience due to the complexity of O(d·2 (1-r)d< ) in existing decoders, which is not feasible for real-time applications.

Innovation Solution

Implementing a low-complexity decoder for GLDPC codes using generalized sum-product and min-sum algorithms, involving vectorization, activation functions, and deep neural networks to reduce complexity to O(d2 p< ), where p is significantly smaller than the component node degree d, and applying multi-dimensional inverse discrete Fourier transforms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional GLDPC decoding algorithms are used, then error correction capability is improved, but computational complexity becomes prohibitively high

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transforms the decoding problem by changing the mathematical domain from time domain to frequency domain using Fourier transforms. This parameter change in the computational approach reduces the complexity from exponential O(2^d) to polynomial O(d^2) while preserving the error correction capability through the mathematical equivalence of the transformations.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the conventional iterative message-passing algorithm (mechanical computational process) with a spectral domain algorithm using Fourier transforms. This substitution fundamentally changes the computational mechanism from sequential iterative updates to parallel frequency-domain operations, dramatically reducing complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If longer codewords are used to improve message to parity bit ratio, then error correction efficiency is improved, but calculation latency increases

Engineering Contradiction:
Improveerror correction efficiencyVSAvoidcalculation latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By transforming to the frequency domain using Fast Fourier Transform, the patent enables efficient processing of long codewords. The FFT algorithm reduces the computational complexity from O(N^2) to O(N log N) where N is the codeword length, thereby reducing calculation latency while maintaining the ability to process longer codewords for improved error correction efficiency.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If high code rates are used with low SNR, then bandwidth efficiency is improved, but decoding reliability deteriorates

Engineering Contradiction:
Improvebandwidth efficiencyVSAvoiddecoding reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces the frequency domain as an intermediary representation between the received noisy signal and the final decoded message. By operating in the frequency domain, the algorithm can more effectively separate signal from noise through spectral analysis, improving decoding reliability under low SNR conditions while maintaining high code rates for bandwidth efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4233177B1Efficient decoding of gldpc codes
Publication Date: 2025.06.25 HUAWEI TECH CO LTD
  • EP4233177B1 patent drawingFigure 1
  • EP4233177B1 patent drawingFigure 2A~2B
  • EP4233177B1 patent drawingFigure 3A~3B

AI summary

A method and a decoder for error correction code, used for digital data over a noisy analog medium, such as a communication or storage medium is disclosed. The decoder comprises one or more computation components adapted for receiving scalars values, representing an estimation of a bit value received through a noisy channel, from a device comprising a compatible encoder. The computation components convert the scalar values, to vectors by an indexing based function, the parity check matrix and the associated scalar value. Followingly, the vectors are processed using an elementwise multiplication. The computation components further generate messages using targeted messages, their corresponding column from the parity check matrix and a fixed location message.