Flexible-Rate GLDPC Encoding with Low Gate Count
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Solution Overview
Problem
Existing GLDPC encoding procedures suffer from high complexity and restrictive constraints, such as high computation and memory complexity, and require codewords to be of identical sizes, limiting their application in storage devices with low ECC redundancy and high code rates.
Innovation Solution
A low-complexity encoding method for GLDPC codewords that allows for different supercode sizes and enables encoding at any rate, using a belief propagation decoder with smaller complexity, and supports the use of any systematic constituent linear block code, including Reed-Muller, BCH, Hadamard, and Hamming codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional GLDPC encoding procedures are used, then error correction capability is improved, but computation complexity increases to O(N^2)
Solution Approach 1:
The patent segments the GLDPC codeword into multiple subcodewords, each protected by a systematic constituent linear block code. This segmentation allows the encoding complexity to be reduced from O(N^2) to O(p·k) by performing independent encoding on smaller subcodewords rather than encoding the entire codeword at once.
Solution Approach 2:
The patent employs a universal systematic constituent linear block code that can be applied to any subcodeword regardless of its position or content. This universal approach using codes such as Reed-Muller, BCH, Hadamard, or Hamming codes simplifies the encoding architecture while maintaining flexible code rates and supercode sizes.
2Reliability
If traditional GLDPC encoding procedures are used, then error correction capability is improved, but memory complexity increases
Solution Approach 1:
By segmenting the codeword into subcodewords and applying systematic constituent linear block codes to each, the patent reduces memory complexity from O(N^2) to O(p·k). The systematic nature of these codes allows for efficient memory usage during encoding operations.
3Device complexity
If low code rate is used, then encoding complexity is reduced, but code rate flexibility is constrained
Solution Approach 1:
The patent implements dynamic code rate adjustment by allowing different numbers of information bits and parity bits in each subcodeword. The code rate can be flexibly configured based on storage device requirements, enabling adaptation to various ECC redundancy levels while maintaining manageable encoding complexity through the systematic constituent linear block code structure.
Data Source
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AI summary
Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.