Glitch Absorption Circuit for Dual-Core Lockstep Reset Faults
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Solution Overview
Problem
Dual-core lockstep systems face reliability issues due to unintended glitches generated during asynchronous reset assertions, which can propagate and cause fake failures, compromising system reliability in safety-critical automotive applications.
Innovation Solution
A glitch absorption device is placed at the end of a fault signal path in a local system before the signal is sent to a global system, utilizing a D-type flip-flop to absorb glitches, ensuring that only valid fault signals are propagated, thereby preventing glitches from affecting the dual-core lockstep system's operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous reset is used to achieve faster data path, then speed is improved, but unintended glitches are generated causing reliability issues
Solution Approach 1:
A glitch absorption device is introduced as an intermediary component between the fault signal path and the dual-core lockstep system. This device captures and absorbs unintended glitches generated during asynchronous reset assertions, preventing them from propagating into the system logic. The intermediary component allows the asynchronous reset to maintain its speed advantage while filtering out harmful glitch signals that would compromise reliability.
2Reliability
If glitch absorption device is added to filter glitches, then reliability is improved, but device complexity increases
Solution Approach 1:
The glitch absorption device is implemented using simple, readily available digital logic components such as D-type flip-flops or basic logic gates. These are inexpensive, well-understood components that can be easily integrated into the existing system without requiring complex or specialized hardware. The solution prioritizes simplicity and cost-effectiveness while achieving the reliability improvement goal.
Data Source
AI summary
An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.