Glitch Suppression Buffers for Dual-Core Lockstep Signal Paths
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Solution Overview
Problem
Dual-core lockstep systems in automotive applications face reliability issues due to undetectable faults on common paths of clock, reset, and test signals, which can cause glitches leading to system crashes.
Innovation Solution
The implementation of glitch suppression buffers at the ends of common signal paths for clock, reset, and test signals before these signals are routed to the main and shadow core processors, effectively suppressing glitches and enhancing fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If timing buffers are placed on common signal paths (clock, reset, test signals), then signal timing is controlled, but glitches are introduced that cause undetectable faults
Solution Approach 1:
A glitch suppression buffer is introduced as an intermediary component between the timing buffer and the dual-core lockstep system. This intermediary buffer suppresses glitches generated by the timing buffer while allowing the timing control function to remain effective, thereby resolving the contradiction between signal timing control and fault detectability
Solution Approach 2:
The signal path is segmented into multiple stages: the original timing buffer stage and a separate glitch suppression buffer stage. This segmentation allows the timing buffer to perform its timing control function while the separate glitch suppression buffer handles the glitch elimination, preventing glitches from propagating to the dual-core lockstep system
2Reliability
If a dual-core lockstep system is used to detect system errors, then crash prevention is improved, but faults on common signal paths remain undetectable
Solution Approach 1:
The glitch suppression buffer acts as an intermediary that prevents glitches on common signal paths from reaching the dual-core lockstep system. By placing this buffer on the common paths, the system maintains its crash prevention capability while making common path faults detectable through the buffer's glitch suppression function
3Reliability
If glitch suppression buffers are added to common signal paths, then fault detectability is improved, but device complexity increases
Solution Approach 1:
The glitch suppression buffer is designed with a universal structure that can be applied to multiple common signal paths (clock, reset, test signals) using the same buffer configuration. This multi-functional approach improves fault detectability across all common paths while minimizing the increase in device complexity by reusing the same buffer design
Data Source
AI summary
An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer, and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.