Glitch Detection at Clock Domain Crossing via Static Analysis
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Solution Overview
Problem
Conventional methods for functional verification of electronic circuit designs, particularly in complex systems with multiple clock domains, often fail to detect glitches at clock domain crossings due to asynchronous signal paths and the error-prone nature of manual inspection, leading to potential logic failures.
Innovation Solution
A design verification tool performs static checks on clock domain crossings to identify combinational logic configurations prone to generating glitches by analyzing signal paths and generating a glitch expression based on input and inverted input signals, using a computing system to determine conditions that allow glitch detection and validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual inspection is used to identify combinational logic capable of inducing glitches, then verification accuracy can be improved, but the process becomes error-prone and time-consuming
Solution Approach 1:
The verification tool automatically performs static checks and generates glitch expressions without requiring manual inspection by verification engineers. The system serves itself by autonomously analyzing clock domain crossings, identifying combinational logic, and detecting potential glitches through automated static analysis techniques.
Solution Approach 2:
The patent replaces the manual mechanical inspection process with an automated computational system. Instead of verification engineers manually examining circuit designs, a computing system implementing a verification tool performs static checks, analyzes signal paths, and generates glitch expressions automatically, substituting human manual labor with machine-based automated verification.
2Measurement precision
If simulators sample signal paths at clock domain crossings, then glitch detection capability is improved, but the asynchronous nature of signal paths makes accurate sampling difficult
Solution Approach 1:
The verification tool performs static checks on the circuit design before simulation to pre-identify clock domain crossings that contain combinational logic in their paths. By performing this analysis in advance, the system prepares glitch expressions that can be evaluated during simulation without requiring complex real-time sampling of asynchronous signal paths.
Solution Approach 2:
The patent introduces glitch expressions as an intermediary mechanism between the circuit design and the simulation process. Instead of directly sampling asynchronous signal paths at clock domain crossings, the verification tool generates glitch expressions that represent potential glitch conditions, which then serve as intermediaries to guide and simplify the simulation sampling process.
3Reliability
If static checks flag every clock domain crossing for manual inspection, then comprehensive coverage is improved, but the process becomes time-consuming and error-prone
Solution Approach 1:
The verification tool extracts and analyzes only the specific portions of clock domain crossings that contain combinational logic capable of inducing glitches. Instead of requiring manual inspection of every clock domain crossing, the system automatically identifies and extracts the relevant combinational logic paths, generating glitch expressions only for those specific locations that pose potential risks.
Solution Approach 2:
The patent changes the parameter of analysis from examining all clock domain crossings to specifically targeting those with combinational logic. The verification tool uses static analysis to determine which clock domain crossings have the potential to generate glitches based on the presence of combinational logic, thereby changing the scope and focus of the verification process to improve efficiency while maintaining reliability.
Data Source
AI summary
This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design. The computing system can identify the combinational logic is configured to generate the output signal based, at least in part, on an input signal and an inversion of the input signal. The computing system can identify conditions that, when satisfied, allow the combinational logic to generate the output signal based, at least in part, on the input signal and the inversion of the input signal, and generate a glitch expression based, at least in part, on the identified conditions. The computing system can determine the combinational logic is configured to generate at least one glitch in the output signal based, at least in part, on the glitch expression.