Glitch Detection Circuit for Simultaneous Clock and Voltage Faults
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional glitch detectors for system-on-chip (SoC) fail to detect clock and voltage glitches effectively due to corruption of reference clock signals and process variations, requiring additional time for voltage glitch detection and inability to simultaneously detect both types of glitches.
Innovation Solution
A glitch detector comprising a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit that generates state signals, reference signals, and glitch signals based on patterns associated with clock and voltage signals, allowing simultaneous detection of clock and voltage glitches without relying on a reference clock signal or trim values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock glitch detector uses a reference clock signal to detect glitches, then it can identify clock anomalies, but it fails when the reference clock signal is corrupted or affected by process variations
Solution Approach 1:
The patent extracts the glitch detection functionality from the reference clock signal dependency. The detector generates internal reference signals from the same clock domain being monitored, eliminating the need for an external corrupted reference signal. This is achieved by creating delayed versions of the clock signal internally and using these for comparison, thus removing the vulnerability to reference signal corruption.
Solution Approach 2:
Instead of using an external reference clock to detect glitches in the system clock, the patent inverts the approach by generating reference signals from the system clock itself through internal delay elements. The detection logic compares the original clock signal with these internally generated delayed signals, reversing the traditional reference architecture to achieve immunity from reference corruption.
2Reliability
If a conventional voltage glitch detector requires trim values from non-volatile memory on startup, then it can detect voltage glitches, but additional time is required to initiate detection
Solution Approach 1:
The patent applies preliminary action by pre-configuring the delay elements with fixed delay values during the design phase, eliminating the need for runtime trimming operations. The delay elements are designed to provide appropriate delay ranges without requiring memory reads or configuration sequences, enabling immediate glitch detection upon clock signal availability.
Solution Approach 2:
The detector circuit serves itself by using internally generated delayed clock signals as references without requiring external trim values or configuration data from non-volatile memory. The circuit autonomously establishes its reference signals and begins detection immediately, eliminating dependency on external configuration resources and reducing initialization time.
3Measurement precision
If separate conventional detectors are used for clock and voltage glitches, then each can detect its specific glitch type, but the system cannot simultaneously detect both types of glitches
Solution Approach 1:
The patent implements a universal glitch detector that performs both clock glitch detection and voltage glitch detection using a single integrated circuit. The detector uses the same delayed signal generation mechanism for both detection functions, allowing simultaneous monitoring of clock signal integrity and voltage signal integrity without requiring separate dedicated detector circuits.
Solution Approach 2:
The patent merges the clock glitch detection functionality and voltage glitch detection functionality into a single integrated detector unit. Both detection paths share the same delay element infrastructure and comparison logic, enabling simultaneous detection of both glitch types from a single clock signal input without the need for separate detector circuits.
4Ease of manufacture
If process variations cause frequency changes in clock signals, then manufacturing tolerances are accommodated, but conventional detectors cannot distinguish between normal variations and actual glitches
Solution Approach 1:
The patent addresses parameter changes by designing delay elements with fixed delay characteristics that are insensitive to process variations. The delay elements are configured to provide consistent time delays across process corners, and the detection logic compares signals with these stable delayed references, enabling distinction between normal process-induced frequency variations and actual glitch events.
Data Source
AI summary
A glitch detector includes a metastability detector circuit, a reference storage circuit, and a pattern comparison circuit. The metastability detector circuit is configured to generate state signals at each cycle of the clock signal. The reference storage circuit is configured to store a logic state of each state signal based on a delayed version of the clock signal, and generate reference signals. A logic state of each reference signal is equal to a logic state of a corresponding state signal generated during a previous cycle of the clock signal. The pattern comparison circuit is configured to receive the state signals generated during a current cycle of the clock signal, the reference signals, and first and second values, and generate clock and voltage glitch signals based on first and second patterns that are associated with the state signals generated during the current cycle and the reference signals, respectively.