Glitch Detection at 50 GSPS Using Phase-Shifted Acquisition
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Solution Overview
Problem
Conventional logic analyzers struggle to detect picosecond-level glitch pulses due to limitations in their operating clock, making it difficult to accurately identify glitches in high-frequency digital systems.
Innovation Solution
A method involving time-interleaved sampling and alternative splicing of data by two acquisition units with a 180° phase difference, followed by equal-interval extraction and exclusive OR operations to identify transition edges and determine glitch positions, enabling detection of glitches at a sampling rate of 50 GSPS with a time interval of 20 ps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional trigger acquisition with timing clock is used, then the system can operate at high frequency, but the detection precision for picosecond-level pulse width deteriorates due to operating clock limitations
Solution Approach 1:
The patent segments the data acquisition process into two independent channels (first acquisition channel and second acquisition channel) with different phase clocks. Each channel operates independently to capture signal transitions, allowing the system to achieve high sampling rates while maintaining precise glitch detection capability through parallel processing of segmented data streams
Solution Approach 2:
The patent introduces a phase dimension by using two acquisition channels with 180° phase difference. This dimensional approach allows simultaneous sampling at high frequency while capturing transition edges that occur between conventional sampling points, thereby achieving both high speed operation and precise picosecond-level glitch detection
2Measurement precision
If the sampling rate is increased to detect narrower pulses, then the glitch detection capability improves, but the system complexity increases due to higher clock requirements
Solution Approach 1:
The patent merges the functionality of two phase-shifted acquisition channels into a unified data processing pipeline. By combining data from both channels through alternative splicing and joint processing, the system achieves high-resolution glitch detection without requiring a single ultra-high-speed clock, thereby reducing overall system complexity while maintaining superior measurement precision
Solution Approach 2:
The patent introduces an intermediary processing stage that receives data from both acquisition channels, performs alternative splicing, and identifies transition edges. This intermediary layer decouples the complexity of high-precision detection from the basic sampling operation, allowing the system to achieve picosecond-level glitch detection without proportionally increasing overall system complexity
Data Source
AI summary
Methods for detecting a glitch at a high sampling rate are provided. In some embodiments, a method includes the following steps: S1, acquiring to-be-identified data; S2, processing the to-be-identified data to obtain normal sampling data; and S3, performing glitch identification on the to-be-identified data to obtain a glitch position of the normal sampling data. In other embodiments, the disclosure provides a system for detecting a glitch at a high sampling rate and for implementing the method for detecting a glitch at a high sampling rate. The system includes an acquisition unit and a glitch identification unit. The acquisition unit acquires and processes the to-be-identified data to obtain the normal sampling data, and the glitch identification unit performs glitch identification on the to-be-identified data to obtain the glitch position of the normal sampling data.