Glitch Detection Circuit for Flip-Flop Reset Paths
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Solution Overview
Problem
Detecting and fixing glitches in digital circuit designs, particularly those causing metastable states due to transitions on reset pins of flip-flops, is challenging due to their short duration and complexity.
Innovation Solution
A method and system that utilize dual-rail encoding to generate a glitch detection circuit, integrated into the circuit design, allowing for simulation or formal verification to identify and evaluate glitches in reset paths through logical equations and Verilog modules, effectively modeling and detecting glitches in reset paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dual-rail encoding is used to generate glitch detection circuit, then glitch detection accuracy is improved, but device complexity increases
Solution Approach 1:
The circuit is divided into sub-circuits, and glitch detection is applied selectively to specific nets that drive flip-flop reset pins. This segmentation allows accurate glitch detection where needed while avoiding unnecessary complexity in other parts of the circuit.
Solution Approach 2:
An intermediary glitch detection circuit is inserted between the sub-circuit and the flip-flop reset pin. This intermediary component monitors for glitches without requiring complete redesign of the entire circuit, thus improving detection accuracy while limiting complexity increase to localized areas.
2Reliability
If glitch detection circuit is integrated into sub-circuit, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
Glitch detection is performed during simulation and formal verification stages before manufacturing. This preliminary detection allows design corrections to be made early in the design process, improving reliability without adding manufacturing complexity since the detection logic is part of the design verification rather than the manufacturing process.
Solution Approach 2:
The glitch detection functionality is implemented as a logical model in simulation/verification environments rather than physical hardware modifications. This copying approach allows comprehensive reliability testing without altering the actual manufacturing process or adding physical manufacturing complexity.
3Measurement precision
If formal verification and simulation are performed on optimized HDL output, then glitch detection capability is improved, but loss of time increases
Solution Approach 1:
Formal verification and simulation are applied selectively to specific sub-circuits and nets rather than the entire design. This segmented verification approach maintains high glitch detection capability for critical reset paths while significantly reducing the total verification time compared to full-design verification.
Solution Approach 2:
The verification process applies partial action by focusing only on the necessary sub-circuits that drive reset pins, using just enough verification effort to detect glitches where they matter most, rather than performing exhaustive verification on the entire design.
Data Source
AI summary
A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the sub-circuit, and performing a simulation or a formal verification of the optimized HDL output file to determine whether a signal associated with the net glitches.