Glitch Detection Circuit Using Transistor Ratio Optimization
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Solution Overview
Problem
Existing glitch detection circuits face challenges in detecting glitches with low power consumption and maintaining detection accuracy across varying temperatures and processes, as they are often affected by current and temperature fluctuations, which can lead to incorrect data or device reset.
Innovation Solution
A glitch detection circuit comprising P-type field effect transistors, current sources, capacitors, and determination circuits, where the channel width-to-length ratio of transistors is optimized to minimize resistance variations, and a current mirror circuit is used to provide bias currents, allowing for efficient detection of both positive and negative glitches with minimal power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional glitch detection circuits are used, then detection capability is provided, but power consumption increases and detection accuracy is affected by temperature and process variations
Solution Approach 1:
The patent changes the physical parameters of the transistor channel (width-to-length ratio) to create different resistance characteristics. By optimizing these geometric parameters, the circuit achieves temperature-compensated operation where the detection threshold remains stable across temperature and process variations, while maintaining low power consumption through proper bias current selection
Solution Approach 2:
The patent uses a current mirror circuit to create a copy of the reference current path. This allows the detection circuit to compare the glitch current against a mirrored reference without requiring additional active power consumption, as the current mirror passively replicates the reference characteristics for comparison purposes
2Measurement precision
If detection sensitivity is increased to detect smaller glitches, then detection capability improves, but the circuit becomes more sensitive to temperature and process variations
Solution Approach 1:
The patent optimizes the channel width-to-length ratio parameters of the transistors to create a detection threshold that is inherently less sensitive to temperature changes. By carefully selecting these geometric parameters, the circuit maintains consistent detection sensitivity across a wide temperature range and process variations
Solution Approach 2:
The patent implements a feedback mechanism where the detection circuit continuously monitors the voltage drop across the transistor and compares it against a reference. This feedback loop allows the circuit to maintain stable detection sensitivity by compensating for temperature and process variations through automatic threshold adjustment
3Stability of the object's composition
If the detection threshold voltage is made fixed, then detection consistency is improved, but the circuit cannot adapt to different operating conditions
Solution Approach 1:
The patent designs the detection circuit to serve multiple functions: it can detect glitches of various magnitudes, operate across different temperature ranges, and function with different power supply voltages. The universal design is achieved through the transistor-based detection mechanism that naturally adapts to different operating conditions while maintaining consistent detection behavior
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables stable and low-power glitch detection that is less affected by temperature and process variations, ensuring consistent detection ranges and preventing device damage from voltage fluctuations.
Implementation Method 1
a capacitor, the other terminal of the capacitor electrically couples to a gate of the P-type field effect transistor and a power supply terminal
Implementation Method 2
The P-type field effect transistor includes a source electrically coupling to a power supply terminal
Data Source
AI summary
A glitch detection circuit includes a first P-type field-effect transistor and a second P-type field-effect transistor which are biased by the same current, and a channel width-to-length ratio of the first P-type field-effect transistor is higher than that of the second P-type field-effect transistor. A capacitor having a terminal grounded and another terminal connected to the gates of the first and second P-type field-effect transistors and a power supply terminal. A determination circuit configured to determine that a negative glitch occurs when a voltage decreasing amount of the drain of the first P-type field-effect transistor is greater than that of the second P-type field-effect transistor, and determine that a positive glitch occurs when an voltage increasing amount of the drain of the second P-type field-effect transistor is greater than that of the first P-type field-effect transistor.