Glitch-Free Clock Frequency Change Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock management techniques for portable electronic devices often introduce transients or glitches when changing the frequency and phase of clock signals, which can disrupt digital circuits and power supplies, leading to inefficient power management and potential system instability.
Innovation Solution
A clock generation circuit that synchronously changes the frequency and phase of output clock signals by dividing a reference clock signal and generating mutually exclusive phase pulses, ensuring that frequency changes only occur when a phase pulse corresponding to the requested phase is asserted and the counter circuit is in a predetermined state, thus preventing glitches or missing pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock frequency is changed using conventional gating techniques, then power consumption is reduced and frequency flexibility is improved, but transients or glitches are introduced that disrupt digital circuits
Solution Approach 1:
The patent applies preliminary action by preparing the clock signal transition in advance through a multi-stage buffer system. The new clock signal is generated and conditioned through multiple buffering stages before being switched to the output, ensuring that the transition is clean and glitch-free. This preliminary preparation of the alternative clock signal path eliminates transients that would otherwise disrupt digital circuits during frequency changes.
Solution Approach 2:
The patent uses intermediary elements in the form of multiple buffer stages (first buffer, second buffer, third buffer) that mediate between the clock signal source and the output. These buffers act as intermediaries that condition and isolate the clock signal transitions, preventing direct glitch propagation to the digital circuits. The intermediary buffers smooth out the frequency transition process.
2Productivity
If clock frequency changes are made rapidly to respond to processing demands, then productivity is improved, but transients are more likely to be introduced causing system instability
Solution Approach 1:
The patent prepares the alternative frequency clock signal in advance through multiple buffering stages before the actual frequency switch occurs. This preliminary action ensures that when a rapid frequency change is needed for productivity, the new signal is already conditioned and ready, allowing fast transitions without introducing transients that would compromise system stability.
Solution Approach 2:
The patent incorporates feedback mechanisms where the clock management circuit monitors processing demands and automatically adjusts clock frequency in response. The system detects when higher processing speed is needed and triggers appropriate frequency changes, balancing productivity requirements with stable operation through controlled frequency transitions.
3Power
If multiple digital circuits are clocked simultaneously at high frequency to meet computational demands, then processing power is improved, but current surges increase battery power consumption
Solution Approach 1:
The patent applies periodic action by implementing duty cycling where digital circuits are alternately activated and placed in sleep mode based on processing demands. Instead of continuously clocking all circuits at high frequency, the system periodically activates only the circuits needed for current tasks, reducing average power consumption while maintaining peak processing power when required.
Solution Approach 2:
The patent uses dynamic clock frequency adjustment where the clock frequency supplied to digital circuits is continuously adapted based on actual processing demands. The clock management circuit monitors circuit activity and adjusts frequencies in real-time, providing high frequency only when computational power is needed, thereby reducing overall battery power consumption while maintaining processing capability.
Data Source
AI summary
A clock generation circuit generates clock signals of a requested frequency and relative phase by dividing a reference clock signal by counting reference clock signal pulses in a counter circuit. The clock generation circuit changes the frequency, and optionally also the phase, of an output clock signal upon request, without generating glitches or missing pulses. The clock generation circuit does not alter the frequency of the output clock signal until a phase pulse associated with the requested phase is asserted, and the counter circuit is in a predetermined state, such as a reset state.