Glitch-Free Clock Circuit for Skew and Jitter Reduction
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Solution Overview
Problem
Semiconductor integrated circuits face issues with clock signal skew and latency, leading to poor jitter characteristics, which can be addressed by implementing a semiconductor circuit that reduces or removes skew.
Innovation Solution
The semiconductor circuit includes a first and second flip-flop, a glitch-free circuit, and an inverter, where the glitch-free circuit determines a voltage level based on the inverted and input clock signals, first and second output signals, and provides power supply and ground voltages to a node without transistors connected to the node, and the inverter outputs an inverted output clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a clock divider is used to generate a clock signal of a specific frequency, then the desired frequency is achieved, but skew and latency are introduced leading to poor jitter characteristics
Solution Approach 1:
A de-skew circuit is introduced as an intermediary component between the clock divider and the output to remove skew and latency. The de-skew circuit includes first and second flip-flops that receive clock signals with different phases, along with control logic that selects and combines their outputs to produce a corrected clock signal with improved jitter characteristics.
Solution Approach 2:
The invention uses an inverted clock signal path in parallel with the normal clock path. The first flip-flop receives the inverted clock signal while the second flip-flop receives the normal clock signal, allowing the circuit to compensate for skew by combining outputs from both paths in a way that cancels out timing errors.
2Reliability
If a de-skew circuit is added to remove skew and improve jitter characteristics, then reliability is improved, but device complexity increases
Solution Approach 1:
The de-skew circuit is segmented into distinct functional blocks: a first flip-flop for the inverted clock path, a second flip-flop for the normal clock path, and control logic for selecting and combining outputs. This segmentation allows each component to be optimized independently and simplifies the overall design and analysis of the complex circuit.
Solution Approach 2:
The flip-flops and control logic serve multiple functions: they act as buffers, phase detectors, and signal selectors simultaneously. This multi-functionality reduces the total number of components needed compared to using separate dedicated circuits for each function, thereby reducing overall device complexity while maintaining reliability improvements.
3Ease of operation
If transistors are connected directly to a node for voltage level determination, then circuit functionality is achieved, but glitches are introduced in the clock signal
Solution Approach 1:
The circuit performs preliminary actions by pre-charging and pre-discharging nodes through controlled transistor switching before the actual voltage level determination. This preliminary action ensures that transistors are in the correct state before switching, preventing glitches and ensuring stable signal transitions in the clock output.
Solution Approach 2:
The circuit incorporates beforehand cushioning by using control logic to ensure smooth transitions between different transistor states. The control logic anticipates potential glitch conditions and applies cushioning measures such as staged switching and controlled charge/discharge paths to prevent signal instability before it can occur.
Data Source
AI summary
A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.