Glitch-Free Clock Switching via Oscillation Detection Logic
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Solution Overview
Problem
Mobile communication devices face inefficiencies in low-power operations due to premature switching of reference clocks, leading to metastability and reduced effectiveness in power conservation, as they struggle to determine the stability of higher-frequency clocks before switching, resulting in early exit from low-power modes and potential instability.
Innovation Solution
The implementation of oscillation detection logic that derives a sampled clock signal from a higher-frequency reference clock, comparing it against a lower-frequency clock to determine stability before switching, ensuring glitch-free transitions and improving the robustness of electronic circuits by avoiding premature switching to unstable clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the electronic circuit switches to the higher-frequency reference clock immediately upon exit from low-power operations, then the processing capability is restored quickly, but the circuit experiences metastability and potential glitches due to the clock being unstable
Solution Approach 1:
The patent applies preliminary action by detecting the stability of the higher-frequency reference clock before the electronic circuit switches to it. The oscillation detection logic monitors the clock signal and only permits switching after the clock has stabilized, preventing metastability and glitches while maintaining quick recovery from low-power operations.
2Reliability
If the electronic circuit waits for the reference clock to fully stabilize before switching, then metastability is avoided, but the circuit must exit low-power operations earlier than needed, reducing power conservation effectiveness
Solution Approach 1:
The patent implements feedback through the oscillation detection logic that continuously monitors the higher-frequency reference clock and provides real-time stability information to the clock switching control logic. This feedback mechanism allows the system to switch clocks as soon as stability is achieved, avoiding both premature switching and excessive waiting, thus optimizing the balance between reliability and power consumption.
3Use of energy by moving object
If the reference clock is switched off during low-power operations to conserve energy, then power consumption is reduced, but the clock requires ramp-up and stabilization time upon reactivation
Solution Approach 1:
The patent applies preliminary action by initiating stability detection of the reference clock as soon as it is activated, before the electronic circuit needs to switch to it. This allows the system to prepare for the switch in advance, minimizing the time loss during clock transitions while maintaining power savings during low-power operations.
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
An electronic circuit is switched from a lower-frequency reference clock to a higher-frequency reference clock. An oscillation detection logic is configured to determine the stability of the higher-frequency reference clock prior to switching the electronic circuit to the higher- frequency reference clock. The oscillation detection logic derives a sampled clock signal from the higher-frequency reference clock, wherein the sampled clock signal has a slower frequency than the lower-frequency reference clock. The oscillation detection logic then compares the sampled clock signal against the lower-frequency reference clock to determine the stability of the higher-frequency reference clock. By deterministically detecting stability of a reference clock prior to switching to the reference clock, it is possible to avoid premature switching to an unstable reference clock, thus providing glitch-free clock switching in the electronic circuit.