Glitch Power Estimation via Replay Simulation
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Solution Overview
Problem
Current EDA systems face challenges in accurately and efficiently performing glitch analysis and power estimation, particularly due to the runtime-intensive and error-prone nature of GLS/SDF simulations, which are often performed too late in the circuit design process, leading to inaccurate power consumption estimates and increased manufacturing costs.
Innovation Solution
A replay-based power analysis method using no-timing simulation tools and automatically generated SDF delay data, which replays pre-existing signal waveforms with delayed signal injection to simulate circuit designs, allowing for early power analysis and hierarchical name rectification using machine learning to address signal name mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If GLS/SDF simulations are performed for glitch analysis and power estimation, then measurement precision is improved, but productivity deteriorates due to runtime-intensive simulations performed too late in the design process
Solution Approach 1:
The patent performs power consumption estimation using glitch analysis at an early stage in the IC design process, before tape-out. By analyzing the circuit design at this preliminary stage using the replay-based method with SDF delay data, the system enables power optimization opportunities that would otherwise be lost, thereby improving productivity without sacrificing measurement precision.
Solution Approach 2:
The patent creates a replay model that copies the behavior of the full GLS/SDF simulation but executes it more efficiently. By replaying simulations with pre-computed SDF delay data applied to RTL or gate-level netlists, the system achieves comparable power estimation accuracy to full GLS/SDF simulations but with significantly reduced runtime, thus resolving the contradiction between precision and productivity.
2Ease of manufacture
If GLS/SDF simulations are used for accurate power estimation, then manufacturing cost is reduced through early optimization, but device complexity increases due to the complexity of performing glitch analysis
Solution Approach 1:
The patent segments the complex GLS/SDF simulation process into manageable components by using pre-computed SDF delay data and replaying simulations on simplified RTL or gate-level netlists. This segmentation allows accurate power estimation without requiring the full complexity of traditional GLS/SDF simulations, making the process more manageable and cost-effective.
Solution Approach 2:
The patent introduces SDF delay data as an intermediary that bridges the gap between simple RTL simulation and complex GLS/SDF simulation. By applying SDF delay information to replayed simulations, the system achieves accurate power estimation without directly executing the computationally intensive GLS/SDF simulation, thereby reducing device complexity while maintaining ease of manufacture benefits.
3Productivity
If replay-based power analysis is performed early in design, then productivity is improved, but measurement precision may deteriorate compared to traditional GLS/SDF simulations
Solution Approach 1:
The patent changes the parameters of the simulation by applying SDF delay data to replayed simulations, transforming them into timing-aware analyses. This parameter change enables the replay-based method to achieve measurement precision comparable to traditional GLS/SDF simulations while maintaining the productivity benefits of earlier execution in the design flow.
Data Source
AI summary
A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.