Glitch PUF Circuit Selection for Semiconductor Reliability
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Solution Overview
Problem
The existing glitch PUF technology in semiconductor devices faces performance issues due to device manufacturing variability and aged deterioration, leading to inconsistent output patterns and reduced information generation, which affects authentication and encryption processes.
Innovation Solution
A device-specific information generation device and method that incorporates multiple glitch generation circuits with a selector and performance evaluation/control unit to select and output glitches that meet desired performance criteria, ensuring consistent performance regardless of manufacturing variations or device aging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single glitch generation circuit is used, then the device complexity is reduced, but the performance consistency and reliability deteriorate due to manufacturing variability and aging
Solution Approach 1:
The glitch generation function is divided into multiple independent sub-circuits (first glitch generation circuit, second glitch generation circuit, etc.), each capable of generating glitches independently. This segmentation allows the system to select from multiple sources, improving reliability while keeping each individual circuit simple.
Solution Approach 2:
Multiple glitch generation circuits are designed with the same functional capability to generate glitches, creating redundancy. The selector circuit enables universal access to multiple glitch sources, ensuring that if one circuit degrades or fails, others can take over, thus improving reliability without significantly increasing overall system complexity.
2Reliability
If multiple glitch generation circuits are used, then the reliability and performance consistency improve, but the device complexity increases
Solution Approach 1:
A selector circuit is introduced as an intermediary component that manages multiple glitch generation circuits. This mediator selects the appropriate glitch signal from multiple sources based on performance evaluation, allowing the system to maintain high reliability while controlling complexity through centralized management rather than distributed complexity.
Solution Approach 2:
The system performs preliminary evaluation of glitch generation performance during manufacturing or initialization, selecting the optimal circuit configuration before actual use. This preliminary action ensures that the system operates with optimal performance from the start, reducing the need for complex runtime adjustments.
3Manufacturing precision
If glitch generation circuits are selected based on performance evaluation, then the information generation quality improves, but the time required for selection and setup increases
Solution Approach 1:
Performance evaluation and selection of optimal glitch generation circuits are performed during the manufacturing process or system initialization phase, rather than during operation. This preliminary action ensures high information generation quality is achieved without causing time loss during actual authentication or encryption operations, as the selection is already completed.
Data Source
AI summary
A device generating specific information of a semiconductor device includes a bit generation unit including a glitch generation circuit and a bit conversion circuit for converting a shape of the glitch into an information bit. The glitch generation circuit includes a plurality of combinational circuits mounted thereon to output a plurality of different glitches. The bit generation unit further includes a selector for selecting one glitch from among the plurality of different glitches in response to a selection signal to output the selected one glitch to the bit conversion circuit. The device further includes a performance evaluation/control unit for outputting the selection signal to obtain a piece of bit information corresponding to each of the plurality of different glitches and specifying a glitch satisfying a desired performance based on the respective pieces of bit information.