Glitch-Based PUF Bit Sequence Generation for FPGA Randomness
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Solution Overview
Problem
The existing PUF circuits using ring oscillators face challenges with alignment and wiring restrictions, leading to low randomness of response bit values and potential design rule violations, particularly in devices with low degrees of freedom like FPGAs, and are prone to reliability issues due to combinational loop circuit designs.
Innovation Solution
A bit sequence generation apparatus that employs a glitch-based approach, utilizing a glitch generating unit, glitch waveform acquisition unit, and bit sequence generating unit to produce highly randomized secret information without violating design rules, by leveraging glitches generated through combinational logic circuits and employing jitter correction processing to accurately acquire and convert glitch shapes into bit sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ring oscillators are used for PUF to generate device-specific identifiers, then device identification capability is improved, but alignment and wiring restrictions reduce the randomness of response bit values
Solution Approach 1:
The patent changes the operating parameters of the ring oscillators by applying different input frequencies to generate glitch patterns. By varying the input frequency parameters, the system extracts multiple bits of information from each oscillator pair, thereby improving the randomness and entropy of the generated identifiers without requiring additional oscillators or complex wiring arrangements.
2Adaptability or versatility
If ring oscillators with same design configuration are used, then device identification is enabled, but alignment freedom restrictions in FPGAs lead to frequency differences dominated by alignment rather than device characteristics
Solution Approach 1:
The patent uses multiple pairs of ring oscillators where each pair serves as a copy of the basic oscillator structure. By using pairs rather than individual oscillators, the system can compare relative frequency differences within each pair while canceling out common alignment and wiring variations, thereby extracting genuine device-specific characteristics without being dominated by placement constraints.
3Adaptability or versatility
If combinational loop circuits like ring oscillators are used, then PUF functionality is achieved, but design rule violations and reliability issues occur
Solution Approach 1:
The patent introduces frequency-to-digital converters and glitch detection circuits as intermediary components that translate the analog frequency differences of the ring oscillators into digital bit sequences. This intermediary approach allows the system to maintain the simplicity of combinational loop circuits while ensuring reliable operation and compliance with design rules by using standard digital logic components for the critical signal processing functions.
Data Source
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AI summary
A bit sequence generation apparatus 200 includes a glitch generating circuit 205 that generates a glitch, a sampling circuit 220 that samples the glitch waveform generated by the glitch generating circuit 205, and a glitch shape determination circuit 211 that generates 1-bit data indicating either 1 or 0, based on the glitch waveform sampled by the sampling circuit 220, and generates a bit sequence composed of a plurality of generated 1-bit data. The bit sequence generation apparatus 200 can provide a PUF circuit that is able to generate highly randomized secret information even in a device with a low degree of freedom of alignment and wiring and that does not violate the design rules.