Glitch PUF Circuit Topology for Stable IoT Security Responses

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Solution Overview

Problem

Traditional PUFs for Internet of Things security are prone to noise and instability due to power supply jitters and are affected by temperature and voltage fluctuations, compromising their reliability.

Innovation Solution

A reliable multi-information entropy PUF is designed with a control circuit, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module, utilizing a fully symmetrical structure to generate and sample glitch signals, which are then processed to produce stable output responses resistant to temperature and voltage fluctuations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a Glitch PUF architecture is used to generate nonlinear glitch waveforms, then resistance to modeling attacks is improved, but stability and reliability deteriorate due to noise from power supply jitters and sensitivity to temperature and voltage fluctuations

Engineering Contradiction:
Improveresistance to modeling attacksVSAvoidstability of output responses
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The PUF system is divided into 128 independent glitch generation circuits, each producing glitch signals that are subsequently processed. This segmentation allows the system to maintain the nonlinear characteristics needed for security while distributing the noise impact across multiple independent units, improving overall stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple glitch signals from 128 separate circuits are combined through a 128-to-1 multiplexer and processed together through the Schmidt sampling module. This merging approach consolidates the individual glitch responses into a unified output that benefits from both the nonlinear security properties and the stabilizing effect of combined signals.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If a fully symmetrical structure is used in glitch generation circuits, then reliability and resistance to temperature/voltage fluctuations are improved, but device complexity increases

Engineering Contradiction:
Improveresistance to temperature and voltage fluctuationsVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

While the glitch generation circuits use symmetrical structures for reliability, the overall system introduces controlled asymmetry through the 128-to-1 multiplexer selection logic and the Schmidt sampling timing, which breaks symmetry in a controlled manner to maintain security while benefiting from the symmetrical building blocks' stability.

Inventive Principle:
Principle #4Asymmetry

3Loss of information

If 128 glitch generation circuits are used to improve randomness and uniqueness, then security is enhanced, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improverandomness and uniqueness of PUF responsesVSAvoidnumber of glitch generation circuits
Core Design Contradiction:
Loss of informationVSDevice complexity

Solution Approach 1:

The system employs a hierarchical structure where 128 individual glitch generation circuits (first level) feed into a 128-to-1 multiplexer (second level), which in turn feeds the Schmidt sampling module (third level). This nested arrangement efficiently manages the complexity by organizing numerous simple units into a structured hierarchy, making the system scalable and manufacturable.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12063038B2Reliable multi-information entropy physical unclonable function (PUF) for internet of things security
Publication Date: 2024.08.13 WENZHOU UNIV
  • US12063038B2 patent drawing
  • US12063038B2 patent drawing
  • US12063038B2 patent drawing

AI summary

A reliable multi-information entropy PUF for Internet of Things security includes a control circuit, a data register, 128 glitch generation circuits, a 128-to-1 multiplexer, and a Schmidt glitch sampling module. The control circuit controls the data register to generate a square signal, the 128 glitch generation circuits to generate glitch signals to be output and the 128-to-1 multiplexer to select the glitch signals to be output. The Schmidt glitch sampling module samples the glitch signals to obtain PUF response outputs. Each glitch generation circuit generates a glitch signal by means of a fully symmetrical structure. The Schmidt glitch sampling module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a buffer module and a D flip-flop.