Glitch Scaler for Logic Gate Power Estimation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power simulation tools face challenges in accurately modeling analog behaviors of glitches in logic simulators, leading to power miscorrelation between pre-silicon estimates and post-silicon measurements in integrated circuit designs, due to the complexity of modern SoCs which exceeds the capacity of these tools.
Innovation Solution
A method involving a glitch scaler that scales glitch widths based on threshold widths and scaling factors to accurately model glitch propagation, filtering, or decay in logic gates, mimicking analog circuit behavior, thereby improving power estimation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power simulation tools are used to model glitch behavior in logic simulators, then power estimation accuracy is improved, but the computational complexity and runtime exceed the capacity for modern SoC designs
Solution Approach 1:
The patent segments glitch analysis into discrete width categories with specific scaling factors. Instead of continuous analog simulation, glitches are divided into segments (width ranges) that can be processed independently by the logic simulator, reducing computational complexity while maintaining power estimation accuracy.
Solution Approach 2:
The patent changes the parameter representation of glitches from continuous analog waveforms to discrete width categories with associated scaling factors. This parameter transformation allows logic simulators to handle glitch data efficiently without requiring full analog simulation capability, resolving the contradiction between accuracy and complexity.
2Reliability
If analog behavior modeling is implemented in logic simulators for accurate glitch analysis, then power miscorrelation is reduced, but the simulator complexity increases beyond practical limits
Solution Approach 1:
The patent creates a simplified copy of analog glitch behavior through scaling factors applied to logic simulator outputs. Instead of implementing full analog simulation, the system copies the essential glitch width information and applies predetermined scaling relationships, achieving power correlation accuracy without analog simulator complexity.
Solution Approach 2:
The patent introduces dynamic scaling factors that adjust glitch width based on categorized ranges. This dynamic adjustment mechanism allows the logic simulator to adaptively model analog-like glitch behavior without requiring static analog circuit implementation, balancing reliability improvement with manageable complexity.
3Reliability
If glitch width is fully propagated in logic simulation, then functional correctness is maintained, but power consumption estimation becomes inaccurate due to unrealistic glitch persistence
Solution Approach 1:
The patent applies partial propagation by selectively scaling glitch widths based on categorized ranges. Instead of fully propagating all glitches (excessive action) or filtering them all (insufficient action), the system applies proportional scaling that partially reduces glitch width, maintaining functional correctness while improving power consumption estimation accuracy.
Data Source
AI summary
A method for modeling glitch of a logic gate is provided. An input glitch with a glitch width is obtained from the logic gate. The glitch width is scaled by a first scaling factor when the glitch width is greater than or equal to a first threshold width. The glitch width is scaled by a second scaling factor when the glitch width is less than the first threshold width and greater than or equal to a second threshold width. An output glitch with the scaled glitch width is provided for the logic gate. The scaled glitch width is greater than 0. The first threshold width is greater than the second threshold width, and the second scaling factor is smaller than the first scaling factor.