Glitch Source Ranking in Circuit Layouts
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Solution Overview
Problem
Glitch power constitutes a significant portion of total power expenditure in logic gates, primarily due to unbalanced delays and glitch propagation, with a small number of sources contributing to the majority of this power, making it difficult to identify and address the root causes effectively.
Innovation Solution
A method for identifying and ranking glitch sources in a circuit layout by tracing glitch pulses from sources to terminuses, calculating power consumption, and reporting on the most impactful sources, allowing designers to focus on reducing power consumption by addressing the most problematic logic gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If designers manually analyze all glitch sources in a circuit layout, then they can identify the root causes of glitch power consumption, but the time and computational resources required become prohibitively large due to the sheer number of glitch sources
Solution Approach 1:
The patent extracts and isolates only the critical glitch sources that contribute significantly to total glitch power consumption. By filtering out minor contributors and focusing exclusively on the top-ranked sources (e.g., top 10% of sources causing 90% of power consumption), the system achieves accurate identification without requiring exhaustive analysis of all glitch sources, thereby reducing analysis time while maintaining measurement precision.
Solution Approach 2:
The patent creates a simplified representation or model of glitch sources ranked by their power consumption contribution. Instead of analyzing the complete complex set of all glitch sources, the system works with a copied subset containing only the most significant sources, enabling faster analysis while preserving the essential information needed for accurate glitch power characterization.
2Loss of energy
If designers address all glitch sources equally, then they can potentially reduce total glitch power, but the effort and resources are wasted on minor sources that contribute negligibly to total power consumption
Solution Approach 1:
The patent applies local quality by treating different glitch sources differently based on their individual contribution to total glitch power. Instead of uniform treatment, the system assigns priority levels and optimization efforts proportional to each source's impact. High-contributing sources receive focused attention and optimization resources, while low-contributing sources are deprioritized, thereby reducing overall glitch power consumption efficiently without wasting resources on negligible sources.
Solution Approach 2:
The patent changes the parameter of optimization priority based on the measured glitch power consumption contribution of each source. By dynamically adjusting which sources are targeted first based on their power impact parameters, the system achieves effective energy reduction while maintaining high design productivity. This parameter-based prioritization ensures that optimization efforts are always directed at the most impactful areas.
3Loss of energy
If the circuit layout is optimized to eliminate all glitches, then glitch power consumption is minimized, but the complexity of the design process and verification increases significantly
Solution Approach 1:
The patent applies partial action by optimizing only the most critical glitch sources rather than attempting to eliminate all glitches in the circuit. By focusing optimization efforts on the top-ranked sources that contribute the majority of glitch power, the system achieves substantial energy reduction without incurring the full complexity costs of complete glitch elimination. This selective approach provides diminishing returns optimization, stopping when the effort required exceeds the benefit gained.
Data Source
AI summary
Glitch source identification and ranking is provided by: identifying a plurality of glitch sources in a circuit layout; back referencing the plurality of glitch sources to corresponding lines in a Resistor Transistor Logic (RTL) file defining the plurality of glitch sources; identifying, in the circuit layout, a plurality of glitch terminuses associated with the plurality of glitch sources; determining a plurality of glitch power consumption values associated with the plurality of glitch sources based on fanouts in the circuit layout extending from the plurality of glitch sources to the plurality of glitch terminuses; ranking, by a processor, the plurality of glitch sources based on corresponding glitch power consumption values of the plurality of glitch power consumption values corresponding to individual glitch sources of the plurality of glitch sources; and reporting the corresponding lines in the RTL file associated with the ranked plurality of glitch sources.