Glitch Suppression Buffers for Dual-Core Lockstep Signal Paths
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Solution Overview
Problem
Dual-core lockstep computer systems experience reliability issues due to undetectable faults on common paths of clock, reset, and test signals, which can cause system crashes if not promptly corrected.
Innovation Solution
Implementing glitch suppression buffers at the ends of common signal paths for clock, reset, and test signals to suppress glitches, reducing the need for delay stage flip-flops and minimizing semiconductor area, while maintaining system reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If timing buffers are placed on clock, reset, and test signals in a dual-core lockstep system, then signal timing is adjusted, but glitches are introduced on common paths that cannot be detected
Solution Approach 1:
A glitch suppression buffer is introduced as an intermediary component between the timing buffers and the dual-core lockstep system inputs. This buffer acts as a mediator that filters out glitches from common path signals while allowing legitimate timing-adjusted signals to pass through, thus resolving the contradiction between signal timing adjustment and fault detectability
2Reliability
If delay stage flip-flops are used to suppress glitches on common paths, then system reliability is improved, but semiconductor area increases
Solution Approach 1:
The glitch suppression function is extracted from the complex delay stage flip-flop structure and implemented using a simpler buffer-based approach. By taking out the essential glitch suppression capability and implementing it with fewer components, the solution maintains reliability while reducing semiconductor area
3Device complexity
If a simple glitch suppression approach is used, then device complexity is reduced, but reliability may be compromised
Solution Approach 1:
The glitch suppression buffer is designed to automatically detect and suppress glitches without requiring complex control logic or external intervention. The buffer self-regulates the common path signals, providing reliable glitch suppression through its inherent circuit characteristics while maintaining simplicity
Data Source
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AI summary
An apparatus (100) includes a main core processor (102) configured to receive a first signal through a first main buffer (111), a second signal through a second main buffer (121), a third signal through a third main buffer (131) and a fourth signal through a fourth main buffer (141), a shadow core processor (104) configured to receive the first signal through a first shadow buffer (211), the second signal through a second shadow buffer (221), the third signal through a third shadow buffer (231) and the fourth signal through a fourth shadow buffer (241), and a first glitch suppression buffer (115) coupled to a common node of an input of the first main buffer (111) and an input of the first shadow buffer (211).