Glitch Suppression Circuit Using RC Filter and Schmitt Trigger
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Solution Overview
Problem
Conventional digital signal processing circuits struggle with effectively suppressing multiple glitches and providing consistent delay, as they often fail to remove subsequent glitches and introduce delay times that depend on the time between glitches and signal transitions, leading to unreliable signal processing, especially in serial communication systems.
Innovation Solution
The integration of two switches with an RC filter and Schmitt trigger circuit, where the switches reset the input node to initial conditions after each glitch, allowing for the independent control of delay time based solely on RC values, and reducing sensitivity to supply voltage and temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deglitching circuits are used, then single glitch suppression is achieved, but multiple glitches cannot be suppressed and delay time varies with glitch timing
Solution Approach 1:
The circuit performs preliminary action by resetting the input node to initial conditions after each glitch detection. The switches are configured to proactively clear the RC filter state following a glitch event, ensuring the circuit is prepared to handle subsequent glitches independently. This preliminary reset action prevents accumulation of glitch effects and maintains consistent delay timing regardless of when additional glitches occur.
2Object-affected harmful factors
If delay time is adjusted for glitch suppression, then glitch filtering is improved, but delay becomes dependent on glitch timing rather than RC values
Solution Approach 1:
The circuit segments the delay function from the glitch suppression function. The RC filter provides fixed delay based solely on R and C values, while the switches provide active glitch suppression by resetting the input node. This segmentation allows each function to operate independently with optimal parameters, ensuring delay time is precisely controlled by RC values rather than being variable based on glitch timing.
3Object-generated harmful factors
If rapid switch operation is used in deglitching circuit, then switching transient glitches are reduced, but circuit complexity increases
Solution Approach 1:
The circuit introduces an intermediary RC filter stage between the input signal and the main processing path. This RC filter acts as a mediator that smooths incoming signals and provides inherent glitch filtering based on its time constant. The switches then operate on this pre-conditioned signal, reducing the severity of switching transients and simplifying the overall circuit design compared to direct switch-based deglitching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses multiple glitches and provides a consistent delay time independent of glitch timing, enhancing signal reliability and reducing the impact of voltage and temperature variations, thereby improving the accuracy of digital signal processing.
Implementation Method 1
an RC filter, which introduces a delay of a predetermined length to a received digital signal
Implementation Method 2
a Schmitt trigger, which suppresses glitches that are present in the received digital signal
Data Source
AI summary
A delay and deglitching circuit suppresses glitches occurring in a received digital signal while introducing a predetermined delay to the signal. The deglitching circuit comprises an RC filter and a Schmitt trigger. A node at the input of the Schmitt trigger fed by the RC filter is pulled to a high supply voltage or a low supply voltage when a glitch is removed or the input signal transitions. By setting the RC filter to initial conditions, multiple glitches can be removed with the same affectivity while reducing a sensitivity of the introduced delay to supply voltage variations.


