Glitch Toggle Rate Estimation for Combinatorial Circuitry
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Solution Overview
Problem
Existing methods for estimating power consumption in programmable logic devices, such as FPGAs, often underestimate or overestimate power needs due to inadequate handling of glitches, which are transient output changes caused by internal signal delays, leading to inaccurate power assessments.
Innovation Solution
A method that calculates an estimated glitch toggle rate by generating Boolean Difference Functions (BDFs) based on functional static probabilities and glitch toggle rates, allowing for a more accurate determination of power consumption without requiring post-routing simulation, using a programmed computing arrangement to output data indicative of the estimated glitch toggle rate and total power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If probabilistic measures for input switching activities are used to estimate power consumption, then the estimation process is simplified, but the accuracy of power consumption estimation deteriorates due to inadequate handling of glitches
Solution Approach 1:
The patent introduces Boolean Difference Functions (BDF) as an intermediary mathematical tool to bridge the gap between simple probabilistic measures and accurate glitch detection. The BDF computes the difference between circuit outputs when inputs change, enabling identification of glitch-prone input combinations without requiring complex simulation. This intermediary approach maintains estimation simplicity while significantly improving accuracy by systematically capturing glitch conditions through algebraic differentiation of the circuit's Boolean function.
2Measurement precision
If post-routing simulation is used to accurately capture glitches, then the accuracy of power consumption estimation improves, but the complexity and time required for the estimation process increases
Solution Approach 1:
The patent performs preliminary computation of Boolean Difference Functions and identification of glitch-prone input combinations before the actual power estimation process. By pre-computing the BDF and determining which input patterns can cause glitches, the method eliminates the need for time-consuming post-routing simulation during the estimation phase. This preliminary action separates the complex analysis work from the final estimation, achieving high accuracy without the computational overhead of extensive simulation.
Solution Approach 2:
The patent extracts the essential glitch-related information from the circuit's Boolean function through algebraic differentiation, separating the glitch detection task from the overall power estimation process. By extracting only the critical information about which input combinations produce glitches (through BDF analysis), the method avoids the need to perform complete post-routing simulation while still capturing all necessary glitch behavior for accurate power estimation.
Data Source
AI summary
Disclosed approaches of determining an estimated glitch toggle rate at an output of a logic circuit include inputting functional static probabilities of combinations of states of the plurality of inputs and a generated glitch toggle rate of the logic circuit. Each functional static probability indicates a probability of the states of the inputs of the combination. For each input of the plurality of inputs to the logic circuit, a Boolean Difference Function (BDF) of the input is generated. A maximum glitch rate, which is the estimated glitch toggle rate, is determined based on the generated glitch toggle rate and the functional static probabilities associated with selected combinations of states of the BDF.