Glitchless Clock Multiplexer for Synchronous and Asynchronous Sources
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Solution Overview
Problem
Existing clock multiplexers face challenges in switching between synchronous and asynchronous clock sources without generating glitches, particularly when the switching latency needs to be minimized, as they often require at least one clock cycle, which can lead to data integrity issues and system malfunctions.
Innovation Solution
A design structure for a glitchless clock multiplexer that categorizes clock sources into asynchronous and synchronous groups, using distinct high-frequency glitchless control blocks for each type to optimize switching latency, allowing for switching within one clock cycle or less by optimizing the timing relationship between input clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional multiplexer is used for clock selection, then the device can switch between multiple clock sources, but glitches are generated on the clock line during switching
Solution Approach 1:
The patent applies preliminary action by delaying the clock signal before multiplication. The delay element introduces a controlled time advance in the signal path, ensuring that the multiplied clock signal is properly synchronized with the original clock edge transitions. This preliminary timing adjustment prevents glitches during clock source switching by aligning the phase relationships between input and output clock signals.
2Object-generated harmful factors
If a glitchless clock multiplexer is used, then glitches are prevented on the clock line, but the switching latency increases to at least one clock cycle
Solution Approach 1:
The patent applies parameter changes by modifying the frequency parameter of the clock signal through multiplication. By multiplying the clock frequency by an integer factor N, the period of the output clock becomes N times shorter than the input clock period. This frequency transformation allows the system to achieve fine-grained timing control and reduces the effective switching latency in terms of output clock cycles, even though the absolute time delay remains comparable to conventional designs.
3Speed
If the clock frequency is multiplied by a large integer factor, then the output clock period becomes very short enabling fast switching, but the delay element requirements become more stringent
Solution Approach 1:
The patent applies segmentation by dividing the clock multiplication function into distinct modular components: a delay element, a multiplication logic unit, and a selection mechanism. This segmentation allows each component to be optimized independently - the delay element can be implemented with standard delay circuits, while the multiplication logic can use simple counter-based or phase-locked loop approaches. The modular structure reduces overall design complexity compared to attempting to implement high-frequency clock generation in a single monolithic circuit.
Data Source
AI summary
A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.