Glitchless Clock Switching via Edge Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital circuit clock switching methods introduce clock cycle dead time, which affects dynamic circuits by causing state loss due to leakage current, and limit clock switching ratio flexibility, especially with aggressive processor designs that require dynamic voltage scaling.
Innovation Solution
A system and method using glitchless clock selection logic that detects clock edge alignments to select a clock signal from multiple sources without introducing dead time, employing a phase lock loop, frequency divider, phase aligner, edge detector, and multiplexer to dynamically switch clock signals based on performance requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a glitchless multiplexer is used to switch between multiple clock drivers, then clock glitches are prevented from reaching device circuitry, but clock cycle dead time is introduced causing state loss in dynamic circuits
Solution Approach 1:
The patent replaces the mechanical switching mechanism of traditional glitchless multiplexers with a phase-aligned clock switching mechanism. By using phase aligners to synchronize clock edges from different sources and an edge detector to identify alignment moments, the system enables seamless clock switching without the need to hold the output stable for extended periods, thereby eliminating dead time while preventing glitches.
Solution Approach 2:
The patent applies preliminary action by pre-aligning the phases of multiple clock signals using phase aligners before switching occurs. The phase alignment process ensures that when the switch between clock drivers happens, the clock edges are already synchronized, preventing glitches from propagating to the output while allowing immediate continuation of clock cycles without dead time.
2Reliability
If a reference clock operating at the lowest common multiple frequency is used to indicate when to change clock signals, then clock switching is synchronized, but clock switching ratio flexibility is limited
Solution Approach 1:
The patent implements dynamics by making the clock switching mechanism adaptive rather than fixed to a specific reference frequency. The phase aligners can dynamically adjust to any clock frequency combination, and the edge detector can identify alignment moments regardless of the underlying reference clock frequency. This enables flexible clock switching ratios while maintaining synchronization, as the system adapts to the actual clock frequencies present rather than being constrained by a predetermined reference.
3Use of energy by moving object
If multiple clock drivers running at different frequencies are used with dynamic voltage scaling, then power consumption is reduced during low-demand intervals, but clock frequency switching introduces glitches on the multiplexer output
Solution Approach 1:
The patent replaces the traditional multiplexer switching mechanism with a phase-aligned clock switching approach. By using phase aligners to synchronize clock edges from different frequency sources and an edge detector to identify precise switching moments, the system enables seamless transitions between clock frequencies without introducing glitches, while still allowing dynamic voltage scaling to reduce power consumption during low-demand intervals.
Data Source
AI summary
A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.