Glitchless High-Speed Phase Selector for Fine PLL Phase Switching
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Solution Overview
Problem
Phase mixers in phase locked loops (PLLs) consume significant area and power and are susceptible to power supply noise-induced jitter, often requiring large phase steps despite the need for fine phase resolution.
Innovation Solution
A phase selector that switches between N high speed clock phases without glitches, using a safe zone technique to ensure seamless phase changes, implemented in a PLL to facilitate spread spectrum and fractional divider ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase mixer is used to implement spread spectrum in a PLL, then fine phase resolution is achieved, but area consumption and power consumption increase significantly
Solution Approach 1:
The phase mixer function is segmented into multiple independent phase selectors, each handling a specific phase of the N-phase clock signal. This segmentation allows the system to achieve fine phase resolution through selective phase switching rather than using a complex continuous phase mixer, thereby reducing area consumption while maintaining precision.
Solution Approach 2:
The invention uses dynamic phase selection where the output phase is dynamically switched between N different phase states based on control signals. This dynamic switching approach replaces the static complex structure of a traditional phase mixer with a more efficient time-multiplexed phase selection mechanism, reducing both area and power consumption.
2Measurement precision
If a phase mixer is used to implement spread spectrum in a PLL, then fine phase resolution is achieved, but susceptibility to power supply noise induced jitter increases
Solution Approach 1:
By segmenting the phase mixing function into discrete phase selectors operating on N-phase clocks, the system reduces the continuous analog-like operation of traditional phase mixers that are highly susceptible to noise. The segmented digital switching approach is inherently more noise-immune while achieving the same phase resolution.
Solution Approach 2:
The invention replaces the traditional analog phase mixer mechanism with a digital phase switching mechanism using N-phase clocks and logic circuits. This substitution from analog to digital domain reduces susceptibility to power supply noise and jitter while maintaining fine phase resolution capability.
3Ease of operation
If traditional phase switching is used in a PLL, then phase changes are implemented, but output glitches occur during phase transitions
Solution Approach 1:
The invention prepares N-phase clock signals in advance, where each phase is pre-generated and buffered. During phase switching, the output continuously connects to one of the pre-prepared phase signals, eliminating the need for real-time signal generation during transitions and preventing glitches. The preliminary preparation of all possible phase states ensures seamless switching.
Solution Approach 2:
The N-phase clock signals serve as intermediaries between the reference clock and the output. Instead of directly switching the reference clock phase, the system uses the pre-generated N-phase clocks as intermediate buffers, allowing clean phase transitions without direct switching of the original clock signal, thereby eliminating glitches.
Data Source
AI summary
A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.