Global Addressable Memory in Programmable Logic Devices
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Solution Overview
Problem
The use of soft logic to move data in and out of distributed memory blocks in programmable logic devices is inefficient in terms of area and performance, limiting system performance, especially as memory size increases.
Innovation Solution
Implementing a global addressable memory scheme using a global address to identify memory blocks and data packets with headers, and utilizing vertical cascade chaining and direct memory access (DMA) functions to improve data movement through Network-on-Chip (NOC) bridges, allowing for high-speed data exchange between programmable logic blocks and memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If soft logic is used to move data in and out of distributed memory blocks, then the memory blocks can be accessed, but the area efficiency and performance deteriorate
Solution Approach 1:
The patent introduces a dedicated memory interface and address decoding circuitry as intermediary components between the soft logic and distributed memory blocks. This intermediary layer handles the complex address decoding and data movement tasks, allowing the soft logic to focus on computational functions while the dedicated interface optimizes memory access efficiency and reduces area overhead.
Solution Approach 2:
The patent segments the memory interface functionality into dedicated components including address decoding circuits, data path multiplexers, and control logic units. This segmentation allows each component to be optimized independently, improving overall data movement efficiency while reducing the total area required compared to a monolithic soft logic implementation.
2Productivity
If soft logic is used to move data in and out of distributed memory blocks, then the memory blocks can be accessed, but the system performance deteriorates
Solution Approach 1:
The dedicated memory interface acts as an intermediary that optimizes the data path between soft logic and memory blocks, implementing efficient data movement protocols and reducing access latency. This specialized interface eliminates the performance overhead associated with general-purpose soft logic handling memory operations.
Solution Approach 2:
The patent implements preliminary address decoding and data path setup through dedicated circuitry before actual data transfer operations. This preliminary action prepares the data path in advance, reducing the time required for actual memory access operations and improving overall system performance.
3Quantity of substance
If memory size increases, then more storage capacity is available, but the inefficiency of soft logic access is amplified
Solution Approach 1:
The patent segments the address decoding functionality into hierarchical levels, with dedicated decoding circuits for different memory regions. This segmentation allows efficient addressing of large memory capacities by breaking down complex address decoding into manageable segments, maintaining access efficiency even as total memory capacity increases.
Solution Approach 2:
The dedicated memory interface serves as an intermediary that scales efficiently with increasing memory capacity. The interface includes configurable address decoding and data path width that can be adapted to larger memory configurations without proportionally increasing access latency, unlike soft logic implementations where access efficiency degrades with size.
Data Source
AI summary
Systems and methods for providing capability of access to distributed memory blocks using a global address scheme in a programmable logic device. Each of the distributed memory blocks includes routing circuitry that receives data, and in a first mode, decodes whether the data is intended for a respective distributed memory block. In a second mode, the data may bypass routing circuitry. Furthermore, the data may be received at the distributed memory block via cascade connections of distributed memory blocks in a column and/or via register in the programmable fabric of the programmable logic device.