Global Bit Line Shielding in Non-Volatile Memory
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Solution Overview
Problem
In NAND-type flash memory devices, the miniaturization of global bit lines increases impedance and capacitance, leading to reduced shielding effectiveness and potential misreading due to coupling noise between adjacent bit lines, necessitating additional page buffers and increasing chip size and cost.
Innovation Solution
A non-volatile semiconductor memory device with a switch component that connects odd and even global bit lines to predetermined power lines, using the same structure as selection gate transistors, to maintain shielding effectiveness without increasing chip size, by positioning the switch component adjacent to the global bit line where data is read and connecting it to the bit line where data is not read.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If global bit lines are miniaturized to increase memory density, then memory capacity is improved, but coupling noise between adjacent bit lines increases causing misreading
Solution Approach 1:
The patent introduces switch components as intermediary elements that connect selected global bit lines to ground. These switch components act as mediators to actively manage and control the electrical state of bit lines, providing a mechanism to eliminate coupling noise between adjacent miniaturized bit lines while maintaining high memory density.
Solution Approach 2:
The patent applies preliminary anti-action by proactively grounding unselected global bit lines through switch components before they can be affected by coupling noise from adjacent active bit lines. This preventive measure counteracts the harmful capacitive coupling effects before they can cause misreading, allowing for reliable operation at miniaturized dimensions.
2Reliability
If additional page buffers are added to mitigate coupling noise, then reading reliability is improved, but chip size and manufacturing cost increase
Solution Approach 1:
The patent merges the noise mitigation function into the existing bit line structure by integrating switch components directly into the global bit line network. This consolidation approach provides reading reliability improvement without requiring separate additional page buffer circuits, thereby avoiding increases in chip size and manufacturing complexity.
Solution Approach 2:
The patent implements self-service by enabling the global bit line structure to actively manage its own noise problems through the switch components. The system uses its existing resources (bit line infrastructure and switch components) to ground and control signal levels, eliminating the need for external additional buffering components and reducing overall device complexity.
Data Source
AI summary
A non-volatile semiconductor memory device is provided so that chip size may not increase and occurrence of misreading induced by capacitance of adjacent global bit lines GBL may be prevented, and includes: a non-volatile memory cell array for recording data by setting a threshold voltage for each memory cell transistor serially connected between selection transistors on terminals of a selected bit line; and a control circuit 11 for reading a bit line and data from the memory cell transistor through a global bit line commonly connected to the bit lines. A ground transistor 23 for connecting the global bit line with a predetermined power line is disposed at a position of the global bit line. The ground transistor 23 activated by the control circuit 11 is adjacent to the global bit line where the data is readout and connected to the global bit line where the data is not readout.