In-Memory Convolution on Global Bit Lines With Standard Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional computer systems face challenges in efficiently performing complex machine learning tasks due to high power consumption and poor performance from multiply-and-accumulate operations, which are not well-suited to conventional hardware architectures.
Innovation Solution
Implementing compute-memory circuits that utilize standard data storage cells and perform computations on global bit lines within memory arrays, eliminating the need for specialized cells and optimizing area efficiency by using techniques such as resistive divider circuits and global bit line operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional computer systems are used to perform multiply-and-accumulate operations for machine learning tasks, then computation can be performed using standard processors, but power consumption is high and performance is poor
Solution Approach 1:
The patent combines memory storage and computation functions into a single integrated structure. Data storage cells store weight values, and the same memory structure performs multiply-and-accumulate operations by activating rows with operand data and accumulating products on bit lines, eliminating the need for separate processing units and reducing data movement between memory and processor.
Solution Approach 2:
The memory circuit performs multiple functions: it stores weight values during idle periods and performs computation operations when activated. The same data storage cells and bit line infrastructure are used for both data retention and arithmetic operations, maximizing resource utilization and reducing overall system power consumption.
2Productivity
If specialized data storage cells are used to perform in-memory computation, then computation efficiency improves, but area efficiency decreases due to the need for specialized cells
Solution Approach 1:
Standard data storage cells are designed to perform both data storage and computation operations. The same memory cells that store weight values are activated to perform multiply-and-accumulate operations, eliminating the need for separate specialized computation cells and maintaining high area efficiency.
Solution Approach 2:
The patent merges storage and computation functionalities into the same physical memory structure. Weight values stored in standard data storage cells are directly used for computation without requiring transfer to or storage in specialized computation units, reducing area overhead while maintaining computational efficiency.
Data Source
AI summary
A compute-memory circuit included in a computer system includes multiple data storage cells and multiplier circuits. The data storage cells store weight values associated with a first operand. The multiplier circuits are coupled to a global bit line and receive the weight values via local bit lines coupled to the data storage cells. Using the received weight values and activation signals indicative of a second operand, the multiplier circuits modify a voltage level of global bit line. The resultant voltage level on the global bit line is indicative of a product of the first and second operands, and can be converted to a digital value using an analog-to-digital converter circuit. By performing computation on global rather than local bit lines, standard data storage cells can be employed, improving the area efficiency of the compute-memory circuit.