Global Current Manager Circuit Allocating Power to Multi-CPU Cores

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Solution Overview

Problem

Power management systems in portable computing devices face challenges in balancing power consumption and performance, as reducing operating voltage to conserve power leads to performance degradation and affects user experience, especially under current and thermal constraints.

Innovation Solution

A global current manager circuit allocates power between multiple CPUs based on total current availability and individual CPU quality-of-service requirements, allowing for proportional current allocation to prioritize high-performance tasks while avoiding excessive current draw, thereby maintaining performance without uniformly reducing voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If operating voltage is reduced to conserve power, then power consumption is reduced, but performance deteriorates and QoS is negatively impacted

Engineering Contradiction:
Improvepower consumptionVSAvoidperformance
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent segments the power management approach by dividing the system into multiple independent CPU cores, each with its own power management capabilities. Instead of uniformly reducing voltage across the entire processor, the system can selectively manage power for individual cores or groups of cores, allowing high-performance tasks to receive adequate power while low-performance tasks consume less power, thus resolving the contradiction between power conservation and performance maintenance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality by allowing different CPU cores to operate at different voltage and frequency levels based on their specific task requirements. High-performance cores can maintain higher operating voltages for demanding tasks, while other cores can operate at lower voltages for less demanding tasks, enabling the system to conserve overall power without uniformly degrading performance across all cores.

Inventive Principle:
Principle #3Local quality

2Temperature

If operating voltage is reduced to manage thermal energy, then thermal generation is reduced, but processing speed decreases and QoS is negatively impacted

Engineering Contradiction:
Improvethermal energyVSAvoidprocessing speed
Core Design Contradiction:
TemperatureVSSpeed

Solution Approach 1:

The patent applies segmentation by dividing the processor into multiple independent cores that can be thermally managed separately. The power management system can identify which cores are generating excessive heat and selectively reduce their operating voltage or frequency, while allowing other cores to maintain higher speeds for critical tasks, thus managing thermal energy without uniformly degrading processing speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamics by enabling real-time adjustment of operating voltage and frequency for individual CPU cores based on thermal conditions and task requirements. The system dynamically monitors thermal states and adapts power delivery to maintain acceptable processing speeds in high-performance cores while allowing speed reductions only in cores where thermal management is prioritized, resolving the contradiction between thermal control and speed maintenance.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If current draw is limited to meet current constraints, then current consumption is controlled, but performance is reduced due to voltage reduction

Engineering Contradiction:
Improvecurrent drawVSAvoidperformance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments current management by allocating specific current budgets to individual CPU cores or task groups rather than uniformly limiting current across the entire processor. This allows the system to prioritize current allocation to cores executing high-performance tasks while limiting current to cores running low-performance tasks, thus controlling overall current draw without uniformly reducing performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting operating voltage and frequency parameters for individual CPU cores based on current availability and task requirements. When current constraints are detected, the system selectively modifies operational parameters for specific cores rather than uniformly reducing parameters across all cores, maintaining performance for critical tasks while controlling overall current consumption.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10831254B2Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements
Publication Date: 2020.11.10 QUALCOMM INC
  • US10831254B2 patent drawing
  • US10831254B2 patent drawing
  • US10831254B2 patent drawing

AI summary

Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.