Global Error Correction via GEC Cache for Memory Reliability

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Solution Overview

Problem

In modern high-performance server systems, memory system reliability is compromised due to errors during memory access operations, and existing error detection and correction mechanisms incur additional overhead and latency, especially with large capacity 3D stacked memory modules or DRAM devices with failed columns, where frequent access to cache lines with failures occurs.

Innovation Solution

A two-tier memory protection mechanism is implemented, comprising local error detection (LED) and global error correction (GEC), where LED information is evaluated during every access to immediately detect errors, and GEC data is stored in a cache to correct errors without additional memory access, reducing overhead and latency by using a GEC cache to retrieve correction data for adjacent cache lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If global error correction data is stored in memory and retrieved for every error correction operation, then error correction capability is provided, but memory access overhead and latency increase significantly

Engineering Contradiction:
Improveerror correction capabilityVSAvoiderror correction latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-fetching and storing global error correction data for adjacent cache lines into the GEC cache during previous memory access operations. This allows the memory controller to retrieve correction data from the cache rather than accessing memory again, thereby reducing error correction latency while maintaining correction capability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces the GEC cache as an intermediary component between memory and the error correction process. This cache stores global error correction data and serves as a buffer that eliminates the need for repeated memory accesses during error correction operations, thus reducing overhead and latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If global error correction data is stored in memory, then error correction is possible, but additional memory access operations are required increasing system overhead

Engineering Contradiction:
Improveerror detection and correctionVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary action by storing global error correction data into the GEC cache during prior memory access operations. When an error is detected, the correction data is already available in the cache, eliminating the need for additional memory access operations and improving system efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses copying by creating a duplicate copy of global error correction data in the GEC cache. This copy serves the same purpose as the original memory-stored data but allows faster access without impacting the original memory storage, thus maintaining error correction capability while reducing overhead.

Inventive Principle:
Principle #26Copying

3Reliability

If error correction data for multiple adjacent cache lines is retrieved, then correction data is available for future errors, but data transmission volume increases

Engineering Contradiction:
Improveerror correction coverageVSAvoiddata transmission volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system applies preliminary action by proactively storing error correction data for multiple adjacent cache lines into the GEC cache during previous access operations. This prepares correction data in advance for potential future errors, expanding error correction coverage while the cache mechanism manages data transmission volume efficiently.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9898365B2Global error correction
Publication Date: 2018.02.20 HEWLETT PACKARD ENTERPRISE DEV LP
  • US9898365B2 patent drawing
  • US9898365B2 patent drawing
  • US9898365B2 patent drawing

AI summary

A method that includes evaluating, with a controller, local error detection (LED) information in response to a first memory access operation is disclosed. The LED information is evaluated per cache line segment of data associated with a rank of a memory. The method further includes determining an error in at least one of the cache line segments based on an error detection code and determining whether global error correction (GEC) data for a first cache line associated with the at least one cache line segment is stored in a GEC cache in the controller. The method also includes correcting the first cache line associated with the at least one cache line segment based on the GEC data retrieved from the GEC cache in the controller without accessing GEC data from a memory.