Global Hard Mask Etch Stop for Semiconductor Interconnects
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Solution Overview
Problem
Existing methods for fabricating semiconductor integrated circuits face challenges in developing improved dielectric and metal interconnection processes and structures, particularly in scaling down to smaller geometries, which increases complexity and requires advancements in wiring and interconnects between transistors and other devices.
Innovation Solution
A method for fabricating semiconductor devices involves forming a global hard mask layer as an etch stop during etching through a dielectric layer to form openings that connect conductive features at different horizontal levels and materials, allowing for robust interconnection with relaxed process constraints and improved process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but processing and manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnection structure into multiple segments including conductive features, dielectric layers, and global hard mask layers. This segmentation allows for simplified fabrication processes at each stage while achieving the overall complex interconnection structure needed for high-density ICs
Solution Approach 2:
The global hard mask layer is formed in advance before the etching process to define the openings. This preliminary action simplifies the subsequent etching step and enables precise formation of interconnection structures without requiring complex real-time process control
2Ease of manufacture
If existing interconnection methods are used for scaling, then manufacturing is simpler, but improved dielectric and metal interconnection processes are not achieved
Solution Approach 1:
The global hard mask layer serves as an intermediary element between the dielectric layers and the etching process. It enables precise formation of openings for interconnections while maintaining manufacturing simplicity through standard deposition and etching processes
Solution Approach 2:
The patent employs parameter changes in the dielectric and conductive materials to optimize interconnection performance. By adjusting material properties and layer parameters, improved interconnection quality is achieved while using conventional fabrication processes
Data Source
AI summary
A method of fabricating a semiconductor integrated circuit (IC) and the corresponding device are disclosed. A high-k/metal gate (HK/MG) and a conductive feature are disposed over a substrate, separated by a first dielectric layer. A global hard mask (GHM) layer is formed over the HK/MG, the conductive feature and the first dielectric layer. A second dielectric layer is then formed over the GHM layer. The second dielectric layer is etched to form a first opening to expose a portion of the HK/MG and a second opening to expose a portion of the conductive feature, by using the GHM layer as an etch stop layer. The GHM layer in the first opening and the second opening is then removed.