Global Interconnect System for Partitionable Engine Resource Sharing
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Solution Overview
Problem
Current processor architectures face inefficiencies in handling multiple threads due to the need for context switching and the overhead of duplicating architecture state elements for each thread, which limits fine-grain parallelism and increases software overhead.
Innovation Solution
A global interconnect system with a front end scheduler, segmented register files, and a fragmented memory subsystem allows for efficient execution of multiple code sequences across multiple engines, enabling virtual cores to share resources and reduce the need for context switching through a non-centralized access process and resource reservation mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If hardware duplicates all architecture state elements for each supported thread, then context switch is eliminated, but area, power and complexity increase
Solution Approach 1:
The architecture state elements are segmented into multiple banks (e.g., first bank, second bank, third bank) that can be selectively accessed. Instead of duplicating all state elements for each thread, the system divides the state storage into segments that can be shared or dedicated based on thread needs, reducing overall hardware complexity while maintaining fast context switching.
Solution Approach 2:
The same architecture state elements are made universal by allowing multiple threads to share the same physical storage resources. The system enables flexible allocation where state banks can serve different threads at different times, eliminating the need for complete duplication while supporting hardware thread awareness.
2Loss of time
If hardware supports multiple context states for limited threads, then context switch is eliminated, but area and power increase due to duplication
Solution Approach 1:
The state storage is divided into segmented banks that can be independently managed. Threads can be allocated to specific banks or share banks dynamically, reducing the need to maintain complete duplicate state sets for each thread and thereby reducing power consumption while maintaining fast context switching capability.
Solution Approach 2:
Instead of creating full copies of architecture state for each thread, the system uses selective copying or sharing of state banks. Threads can share common state resources and only maintain unique state when necessary, significantly reducing the area and power requirements compared to full duplication.
3Adaptability or versatility
If number of software threads exceeds hardware threads, then context switch must be performed, but fine grain parallelism is not efficiently supported
Solution Approach 1:
The system dynamically allocates and shares architecture state banks among threads based on runtime needs. This dynamic approach allows the hardware to efficiently support a large number of software threads by flexibly managing state resources, enabling fine-grain parallelism without requiring static duplication of state for each potential thread.
Solution Approach 2:
The system changes the parameter of state allocation from static duplication to dynamic sharing. By allowing threads to share state banks and dynamically allocate resources, the architecture can support far more threads than the number of physical banks, enabling efficient fine-grain parallelism while maintaining hardware thread awareness.
Data Source
AI summary
A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code sequences and a plurality of engines for implementing the execution of the multiple code sequences. A plurality of resource consumers are within each of the plurality of engines. A global interconnect structure is coupled to the plurality of resource consumers and coupled to the plurality of resources to enable data access and execution of the multiple code sequences, wherein the resource consumers access the resources through a per cycle utilization of the global interconnect structure.