Global Interrupt Number Space with Shared Pending Status Memory
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Solution Overview
Problem
Current data processing systems face inefficiencies and increased overhead when handling a large number of processors and interrupts, particularly in scenarios where processors are dynamically powered up or down, leading to excessive circuit area and power consumption due to the need for extensive storage resources for buffering pending interrupts.
Innovation Solution
Implementing a global interrupt number space shared among processors, with pending status data stored in a global memory and cached locally at each processor, allowing for efficient handling and reassignment of interrupts through interrupt translation circuitry and caching mechanisms, which reduces power consumption and speeds up operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processor is provided with extensive storage resources (registers) for buffering pending interrupts from all other processors, then the system can handle the scenario where all processors shut down and transfer responsibility to a single processor, but this leads to excessive circuit area and power consumption
Solution Approach 1:
The patent merges the interrupt buffering function from individual processor registers into a shared memory resource that is collectively accessed by all processors. This consolidation eliminates the need for each processor to have extensive local storage, thereby reducing total circuit area while maintaining the ability to handle interrupt overflow scenarios.
Solution Approach 2:
The shared memory resource serves multiple purposes: it acts as the interrupt translation lookup table, buffers pending interrupts for all processors, and provides a common interrupt handling facility. This multi-functional approach replaces the dedicated extensive registers that would otherwise be required at each processor.
2Reliability
If each processor is provided with extensive storage resources (registers) for buffering pending interrupts from all other processors, then the system can handle the scenario where all processors shut down and transfer responsibility to a single processor, but this leads to increased power consumption
Solution Approach 1:
The patent merges the interrupt buffering function from individual processor registers into a shared memory resource that is collectively accessed by all processors. This consolidation eliminates the need for each processor to have extensive local storage, thereby reducing total circuit area while maintaining the ability to handle interrupt overflow scenarios.
Solution Approach 2:
The shared memory resource serves multiple purposes: it acts as the interrupt translation lookup table, buffers pending interrupts for all processors, and provides a common interrupt handling facility. This multi-functional approach replaces the dedicated extensive registers that would otherwise be required at each processor.
3Area of stationary object
If a global interrupt number space is implemented with shared memory and caching, then power consumption and circuit area are reduced, but complex interrupt translation circuitry and caching mechanisms are required
Solution Approach 1:
The patent pre-loads and caches interrupt translation data in local processor caches before it is needed. This preliminary action allows the complex translation information to be prepared in advance in a decentralized manner, reducing the real-time complexity burden on the main interrupt translation circuitry.
Solution Approach 2:
The patent segments the global interrupt translation functionality into distributed cache structures at each processor, rather than requiring a single centralized translation unit. This segmentation distributes the complexity across multiple simple local components, reducing the complexity of any single circuit block.
Data Source
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AI summary
A global interrupt number space (38) is provided for use in message signalled interrupts. Interrupt destinations (10, 12, 14, 16) are provided with pending interrupt caches (24) with either backing storage provided by global pending status memory (34) shared by all the caches or separate individual pending status memories (56). The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.