Global Link Gate-Cut Structure for Tight IC Contact Spacing
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern features, leading to a trade-off between critical dimension and spacing.
Innovation Solution
The implementation of a metal gate process with trench contact cuts, utilizing a unified dielectric cut plug structure and a 'plug-last' approach to simplify the fabrication process, reducing process variation and improving robustness by avoiding complex plug removal methods, and enabling seamless work function metal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional multi-gate transistor fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and fabrication complexity is lowered, but device performance in terms of mobility improvement and short channel control deteriorates at dimensions below 10 nanometer node
Solution Approach 1:
The patent segments the gate structure into multiple gates surrounding the channel (multi-gate configuration), which divides the control function across multiple gate regions. This segmentation enables improved short channel control by providing better electrostatic control over the channel, while still using conventional bulk silicon substrate fabrication processes to maintain manufacturing simplicity.
2Productivity
If device dimensions are scaled down to increase functional unit density, then capacity is increased, but the trade-off between critical dimension and lithographic spacing constraints worsens
Solution Approach 1:
The patent transitions from planar 2D device architecture to three-dimensional multi-gate structures (such as tri-gate or nanowire configurations). This dimensional change allows increased functional density by utilizing vertical space and multiple gate surfaces, thereby achieving higher device density while working around lithographic spacing constraints through enhanced spatial utilization.
3Reliability
If trench contact cuts with unified dielectric cut plug structure are implemented, then process variation is reduced and robustness is improved, but process complexity increases
Solution Approach 1:
The patent merges the trench contact formation and gate cut operations into a unified process using a single dielectric cut plug structure. By combining these previously separate fabrication steps into one integrated operation, the patent reduces process variation and improves robustness while actually simplifying the overall fabrication process rather than increasing complexity.
Data Source
AI summary
Integrated circuit structures having global links for uniform grid metal gate and trench contact cut are described. A structure includes a dielectric sidewall spacer between a gate electrode and a conductive trench contact. First and second parallel dielectric cut plug structures extend through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The second dielectric cut plug has a recess laterally adjacent to the conductive trench contact and exposing a side of the conductive trench contact. A conductive link is in the recess of the second dielectric cut plug structure, the conductive link in contact with the side of the conductive trench contact, and the conductive link extending along a top surface of the conductive trench contact.