Global Mistracking Analysis for IC Timing Signoff
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Solution Overview
Problem
Current IC design technologies face inaccuracies and overdesign due to pessimistic timing assumptions in static timing analysis, leading to inefficiencies in performance, power, and area, and fail to accurately model global mistracking caused by process variations, which can result in unsafe signoff and limited clock speeds.
Innovation Solution
The proposed solution involves a global mistracking analysis technique that uses variation models to assign parameter variations to classes of circuit elements, computes timing slack, and constructs a timing-slack-sensitivity model to predict the impact of global variations, allowing for accurate and efficient modeling of process variations and reducing timing pessimism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pessimistic timing assumptions are used in static timing analysis, then timing safety is improved, but performance and area efficiency deteriorate due to overdesign
Solution Approach 1:
The patent changes the timing analysis parameters from pessimistic fixed assumptions to dynamic parameters based on actual process variations. By modeling global mistracking with statistical distributions and computing timing slack with correlation effects, the analysis adapts parameters to reflect real manufacturing variations rather than using conservative fixed values, thereby improving performance efficiency while maintaining timing safety
Solution Approach 2:
The patent introduces feedback mechanisms by using measured process variation data to refine timing analysis. The global mistracking model incorporates actual correlation data from process variations, creating a feedback loop where manufacturing data improves timing analysis accuracy, reducing overdesign while preserving reliability
2Reliability
If pessimistic timing assumptions are used in static timing analysis, then timing safety is improved, but area efficiency deteriorates due to overdesign
Solution Approach 1:
The patent changes timing analysis parameters from conservative fixed values to dynamic values based on process variation modeling. By using statistical models that capture global mistracking effects and correlation between timing paths, the area requirements are optimized to match actual needs rather than pessimistic estimates, improving area efficiency while maintaining timing safety
3Device complexity
If global mistracking is not accurately modeled, then manufacturing complexity is reduced, but signoff safety deteriorates
Solution Approach 1:
The patent segments the timing analysis into distinct components: global variation modeling, local variation modeling, and correlation analysis. By dividing the complex global mistracking problem into manageable segments with specific models for each, the patent achieves accurate signoff safety while keeping the overall manufacturing complexity manageable through structured decomposition
Solution Approach 2:
The patent introduces intermediary models and methodologies to bridge the gap between complex physical phenomena and practical analysis. The global mistracking model acts as an intermediary that translates complex process variation effects into usable timing analysis parameters, achieving signoff safety without requiring direct modeling of all underlying physical complexities
4Productivity
If clock speed is increased without accurate global variation modeling, then productivity is improved, but timing accuracy deteriorates leading to unsafe signoff
Solution Approach 1:
The patent enables higher clock speeds by dynamically adjusting timing analysis parameters based on actual process variations. The global mistracking model provides accurate timing predictions that reflect real manufacturing conditions, allowing designers to push clock speeds higher without sacrificing timing accuracy or signoff safety
Data Source
AI summary
For each circuit element in a pair of launch and capture paths, a parameter value of the circuit element may be modified by a variation amount that is assigned to a class of circuit elements to which the circuit element belongs. Next, a timing slack may be computed for the pair of launch and capture paths.