Global Persistent Memory for Cluster Data Coherency

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Solution Overview

Problem

In multi-node systems, high latency and inconsistency of data across nodes due to message passing through I/O drivers lead to cluster failures and high maintenance costs, as each node is managed individually, and existing solutions do not effectively ensure data coherency across nodes.

Innovation Solution

Implementing a global persistent memory with a reflected memory region and a semaphore memory region, accessed using I/O and memory semantics, and utilizing a low-latency fabric with load store semantics to ensure data coherency, where nodes can access shared memory independently and maintain fault isolation boundaries, even in the event of node failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If message passing through I/O drivers is used to access memory across nodes, then nodes can share memory, but high latency and data inconsistency occur

Engineering Contradiction:

Improvedata coherencyVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces a global persistent memory as an intermediary shared resource that all nodes can access directly through the fabric interconnect, eliminating the need for message passing through I/O drivers. This mediator enables direct memory access while maintaining data coherency across nodes, resolving the latency and consistency issues of the previous approach.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent merges the memory access paths of multiple nodes into a unified global persistent memory space accessible through a common fabric interconnect. By combining individual node memories into a shared global memory system, the patent enables direct access without message passing, reducing latency while maintaining data coherency through hardware-supported consistency models.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If individual node management is used, then nodes operate independently, but cluster failure risk increases and maintenance costs rise

Engineering Contradiction:

Improvenode independenceVSAvoidcluster failure risk

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the cluster into independent fault domains where each node operates autonomously with its own local memory and processing units, while sharing a global persistent memory. This segmentation allows individual nodes to fail without affecting the entire cluster, as other nodes can continue accessing the global memory independently, thereby reducing cluster failure risk while maintaining node independence.

Inventive Principle:

Principle #1Segmentation

3Reliability

If global persistent memory is implemented, then data coherency is improved, but system complexity increases

Engineering Contradiction:

Improvedata coherencyVSAvoidsystem complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex software-based memory management and coherency protocols with hardware-supported mechanisms in the fabric interconnect and global persistent memory controller. By substituting mechanical/software complexity with hardware-level support for direct memory access and coherency, the system achieves data consistency while reducing overall system complexity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10296399B2Data coherency model and protocol at cluster level

Publication Date: 2019.05.21 INTEL CORP

AI summary

An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.