Global Planarization Coating for Low-Bias Microelectronic Topography
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Solution Overview
Problem
Current methods for global planarization in microelectronic device fabrication, such as chemical mechanical polishing (CMP), are inefficient and introduce contamination, while existing spin-coated materials struggle to achieve uniformity across substrates with high-aspect-ratio topography, leading to challenges in achieving precise layering for photolithography.
Innovation Solution
A method involving a crosslinking modifier composition applied to a substrate, followed by a planarizing composition, where a crosslinking modification component is generated in situ to reduce crosslinking in the planarizing layer, allowing for solvent-induced thickness reduction, resulting in a non-patterned planarizing layer with minimal bias between dense and isolated topographic features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used to planarize semiconductor device layers, then planarization can be achieved, but the process is time consuming and adds to the expense of device manufacture
Solution Approach 1:
The patent replaces the mechanical CMP process with a chemical solution-based planarization method. A planarizing composition is spin-coated onto the substrate, forming a planarizing layer that is then treated with a solvent to achieve the desired planarization without mechanical contact, thereby eliminating the time-consuming and expensive CMP step while maintaining planarization quality
Solution Approach 2:
The patent changes the physical and chemical parameters of the planarizing layer by controlling the solvent treatment process. By adjusting solvent type, treatment time, and temperature, the layer thickness is modified to achieve optimal planarization, replacing the need for mechanical removal processes
2Manufacturing precision
If chemical mechanical polishing (CMP) is used to planarize semiconductor device layers, then planarization can be achieved, but CMP introduces contamination and other undesirable defects
Solution Approach 1:
The patent eliminates mechanical contact by replacing CMP with a chemical planarization process. The planarizing layer is formed by spin-coating and then treated with solvent, which chemically modifies the layer to achieve planarization without introducing mechanical contamination or defects associated with polishing pads and slurry
3Manufacturing precision
If a thick coating of planarizing material is applied over topographic structures to obtain a planar top surface, then planarization is achieved, but a large overburden is undesirable for further processing steps
Solution Approach 1:
The patent precisely controls the thickness of the planarizing layer by adjusting spin-coating parameters (speed, time, viscosity) and solvent treatment conditions. This allows formation of a planar surface with minimal excess thickness, avoiding the large overburden problem while maintaining sufficient planarity for subsequent processing steps
4Volume of moving object
If other planarizing materials and processes are used to achieve planarization without leaving an excess overburden, then overburden is reduced, but multiple additional steps such as reflow baking or plasma etch back are required
Solution Approach 1:
The patent combines the planarization function with the existing spin-coating and solvent treatment processes already used in semiconductor fabrication. By integrating planarization into these existing process steps rather than adding separate reflow baking or plasma etch back steps, the method reduces overburden while avoiding increased process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient global planarization with reduced thickness variation and contamination, eliminating the need for additional polishing steps, thereby simplifying and cost-reducing the microelectronic device fabrication process.
Implementation Method 1
heating the planarizing composition to form a planarizing layer
Implementation Method 2
applying a planarizing composition on the crosslinking modifier layer; heating the planarizing composition to form a planarizing layer
Implementation Method 3
contacting the planarizing layer with a solvent to reduce the first average thickness and the second average thickness
Data Source
AI summary
Compositions and methods for global planarization of microelectronic substrates are provided. The methods include applying a crosslinking modifier composition to the surface of a substrate, or to any intermediate layer(s) on the substrate surface. A planarizing material can then be applied to the crosslinking modifier layer, which influences the degree of crosslinking in the planarizing layer. Depending on the specific topography of the underlying substrate (or intermediate layer), different amounts of planarizing material are removed during a subsequent develop back step, thereby eliminating bias that usually exists between regions of varying topographic density. The result is an effective global planarization method that is both time and cost efficient.