Global PLL Delay Compensation for Rapid Frequency Tracking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Loop delay in timing control loops of phase-locked loop (PLL) systems degrades system performance, particularly in data storage applications, and existing delay compensation methods assume a constant frequency offset, limiting their effectiveness in tracking rapid frequency variations.
Innovation Solution
A global PLL circuit with a delay compensation circuit that combines error signals from multiple channels and applies a correction term based on current phase and frequency estimates, allowing for accurate tracking of frequency variations without assuming a specific frequency offset model, and is applicable to multi-channel applications like tape systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay compensation is implemented using a prediction element assuming constant frequency offset, then loop delay is compensated, but tracking capability is limited when frequency varies rapidly
Solution Approach 1:
The patent implements a delay compensation filter with adaptive coefficients that dynamically adjust based on the actual frequency variations in the signal. Instead of assuming constant frequency offset, the system continuously adapts to track rapid frequency changes, resolving the contradiction between delay compensation accuracy and tracking capability.
Solution Approach 2:
The system uses feedback from the phase error signal and frequency estimates to continuously update the delay compensation filter coefficients. This feedback mechanism enables the system to maintain accurate delay compensation while adapting to rapid frequency variations, simultaneously improving both reliability and adaptability.
2Reliability
If loop delay is minimized through design, then PLL phase margin is maximized, but implementation and architectural constraints introduce substantial delay
Solution Approach 1:
The patent extracts the delay compensation function into a separate, dedicated filter module with adaptive coefficients. This allows the main PLL circuit to maintain minimal delay for optimal phase margin, while the extracted delay compensation element handles the delay correction without adding significant complexity to the core timing loop.
Solution Approach 2:
The adaptive delay compensation filter acts as an intermediary element that compensates for loop delay without requiring changes to the core PLL architecture. This mediator approach maintains the original PLL phase margin while correcting delay effects, avoiding the complexity increase that would result from redesigning the entire timing loop circuit.
3Reliability
If decisions are taken from sequence detector rather than slicer, then decision reliability is improved, but additional decision delay is introduced
Solution Approach 1:
The patent implements preliminary delay compensation by estimating and correcting for the decision delay introduced by the sequence detector before the timing control decisions are made. This preliminary action removes the time loss effect while preserving the reliability benefit of using sequence detector decisions.
Solution Approach 2:
The system replaces the physical timing reference based on slicer decisions with a compensated timing reference that accounts for sequence detector delay. This substitution maintains decision reliability while eliminating the time loss through mathematical compensation rather than physical timing adjustment.
Data Source
Figure 1
Figure 2~2A
Figure 2B~2C
AI summary
A system in one embodiment includes a global PLL circuit comprising multiple inputs, each input being for receiving an error signal associated with an individual channel; and a delay compensation circuit coupled to the global PLL circuit. A method in one embodiment includes receiving multiple error signals, each error signal being associated with an individual channel; applying one or more delay compensation signals to the error signals; and outputting phase error output signals for each of the channels.