Global Low Power Detection Circuit for Multithreaded Processor Leakage
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Solution Overview
Problem
Portable digital devices with digital signal processors face power leakage issues even when in standby mode due to resource constraints and limited battery life, necessitating an efficient power control method.
Innovation Solution
A multithreaded processor device with a global low power detection circuit that evaluates the activity level of each program thread and selectively controls power to global resources, turning them off when all threads are in sleep mode and restoring power before it's needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the digital signal processor is powered down in standby mode, then power consumption is reduced, but power leakage still occurs due to components continuing to drain energy
Solution Approach 1:
The patent implements dynamic power management by allowing the digital signal processor to operate in multiple power states (fully powered, partially powered, and powered down) rather than a fixed state. The controller dynamically transitions between these states based on activity detection, enabling the system to adapt its power consumption to actual operational needs and minimize leakage during standby periods.
Solution Approach 2:
The patent segments the digital signal processor into multiple independently controllable components or modules. Instead of powering down the entire processor as a single unit, the system can selectively power down specific segments or functional units while maintaining others in a lower-power state, thereby reducing overall power leakage while preserving essential standby functionality.
2Productivity
If multiple program threads are executed simultaneously, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by allowing only the necessary number of program threads to execute simultaneously based on current workload demands. The controller monitors system activity and dynamically adjusts the number of active threads, enabling full multi-threaded processing capability when needed while reducing to fewer or no active threads during low-activity periods, thereby optimizing the balance between productivity and power consumption.
Data Source
AI summary
A multithreaded processor device is disclosed and includes a plurality of execution units to execute a plurality of program threads and includes a global low power detection circuit. The global low power detection circuit includes an input that is responsive to each of the plurality of program threads. The input indicates an execution activity level for each of the plurality of program threads. The global low power detection circuit further comprises logic to evaluate the activity level of each of the plurality of program threads. The logic provides a power level signal. Additionally, the global low power detection circuit includes an output that is responsive to the power level signal. The output is coupled to one or more global resources within the multithreaded processor and the output selectively controls an amount of power provided to the one or more global resources.