Global Routing Capacity Model for Wire Track Segmentation
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Solution Overview
Problem
The existing capacity models used in electronic design automation (EDA) tools for global routing in semiconductor manufacturing, such as the Self Aligned Double Patterning (SADP) process, are inadequate as they rely on simplified measures of wiring capacities and do not accurately account for regional wire track patterns, leading to inefficiencies and inaccuracies in wire routing.
Innovation Solution
A 3D global routing mechanism that determines edge capacities for both minimum and non-minimum width wire tracks separately, using vectors to represent the capacity of each type of wire track and via stack, allowing for precise modeling of wire and via capacities across and between global tiles, which are then used to guide the global routing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a simplified capacity model is used for global routing, then the routing process is faster and simpler, but the accuracy of wire capacity modeling deteriorates
Solution Approach 1:
The patent segments the wire capacity modeling by separating minimum width wire tracks from non-minimum width wire tracks into distinct capacity models. This segmentation allows each type of wire track to be modeled with appropriate precision while maintaining overall routing efficiency. The global router determines edge capacities separately for minimum width wires and non-minimum width wires, avoiding the need for a single complex model that would slow down routing.
Solution Approach 2:
The patent applies local quality by using different capacity modeling approaches for different regions and wire track types. Specifically, it models minimum width wire tracks with one capacity model and non-minimum width wire tracks with another capacity model, allowing each local region to be modeled with the appropriate level of detail and accuracy for its specific requirements.
2Measurement precision
If separate capacity models are used for minimum and non-minimum width wire tracks, then modeling accuracy improves, but device complexity increases
Solution Approach 1:
The patent implements universality by creating a multi-functional capacity modeling system that handles both minimum width and non-minimum width wire tracks through a unified global routing framework. The separate capacity models serve multiple purposes: they provide accurate modeling for different wire types while being integrated into a single routing process that can handle all wire track types consistently.
Solution Approach 2:
The patent applies parameter changes by modifying the capacity model parameters based on wire track width. Instead of using a single set of parameters for all wire tracks, the system changes the capacity model parameters to reflect the specific characteristics of minimum width versus non-minimum width wire tracks, enabling accurate modeling without requiring entirely separate routing systems.
3Manufacturing precision
If detailed capacity information is provided for each wire and via type, then routing accuracy improves, but computation time increases
Solution Approach 1:
The patent applies preliminary action by pre-determining the edge capacities for minimum width wire tracks and non-minimum width wire tracks before the actual routing process. The global router calculates and stores capacity values for all edges in the routing graph in advance, organizing them by wire track type. This preliminary computation allows the routing algorithm to quickly access pre-computed capacity information during route finding, avoiding repeated calculations and reducing overall computation time.
Data Source
AI summary
A global router determines edge capacity of global tiles for a first integrated circuit in a global routing operation. The global router determines a respective edge capacity of first width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit in a first global routing operation. The global router determines a respective edge capacity of second width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit in a second global routing operation. The edge capacities for first width and second width wire tracks are determined in separate operations by the global router as part of the operations performed for fabrication of the first integrated circuit.