Global Shutter Image Sensor Pixel With Buried Channel Memory Node
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Solution Overview
Problem
Conventional CMOS image sensors with global shutter (GS) technology face challenges in reducing noise and image distortion during readout, particularly due to parasitic charge generation and recombination, especially in low-light conditions and when capturing highly dynamic events, as existing approaches fail to achieve optimal performance with available power supply voltages and introduce additional design complexities.
Innovation Solution
The implementation of a GS CMOS image sensor with n-type photodiodes and memory nodes formed in n-doped regions separated by a p-doped vertical barrier layer, which controls electron overflow and generates intrinsic lateral electric fields to facilitate efficient charge transfer and reduce dark current, allowing for lower operating voltages and improved charge transfer efficiency without the need for a global photodiode reset transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional global shutter CMOS image sensors are used, then charge transfer efficiency is improved, but noise and image distortion increase during readout
Solution Approach 1:
The pixel structure is segmented into distinct functional regions: photodiode region for charge generation, memory node region for charge storage, and floating diffusion region for charge readout. This segmentation allows optimized charge transfer paths and isolation of functions to reduce noise and distortion during readout operations.
Solution Approach 2:
Different doping concentrations are applied to different regions: the photodiode uses one doping level, the memory node uses a different doping level, and the floating diffusion uses yet another. This local quality variation optimizes charge transfer efficiency in each region while minimizing parasitic effects and noise generation.
2Adaptability or versatility
If additional transistors are added to achieve global shutter functionality, then image capture capability is improved, but device complexity increases
Solution Approach 1:
The memory node structure serves multiple functions: it acts as a charge storage element during global shutter operation, a transfer node between photodiode and floating diffusion, and a potential reset element. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall device complexity.
Solution Approach 2:
The patent combines the memory node and floating diffusion into a single continuous n-doped region rather than separating them into distinct structures. This merging simplifies the device architecture while maintaining global shutter functionality through controlled charge transfer between the photodiode and the combined memory-floating diffusion region.
3Speed
If higher power supply voltages are used, then charge transfer speed is improved, but power consumption increases
Solution Approach 1:
The patent optimizes the doping concentrations in the photodiode, memory node, and floating diffusion to create favorable potential gradients that enhance charge transfer efficiency. By carefully selecting doping levels, the system achieves rapid charge transfer at lower voltage levels, reducing power consumption while maintaining high transfer speeds.
Solution Approach 2:
The patent replaces voltage-driven charge transfer with diffusion-based charge transfer mechanisms. The concentration gradients created by different doping levels drive charge carriers through diffusion, eliminating the need for high voltage pulses and significantly reducing power consumption while maintaining transfer speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances low-noise, full-charge-readout operations, reduces image distortion, and enables superior charge transfer efficiency between photodiodes, memory nodes, and floating diffusions, supporting faster readout and lower power consumption, while maintaining image quality across the entire pixel array.
Implementation Method 1
which controls electron overflow and generates intrinsic lateral electric fields to facilitate efficient charge transfer
Implementation Method 2
n-type photodiodes... capable of converting a portion of an optical image into an electronic signal
Implementation Method 3
n-doped regions separated by a p-doped vertical barrier layer, which controls electron overflow
Data Source
AI summary
A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated n-doped epitaxial layer regions that are separated from the bulk substrate by a p-type vertical (potential) barrier implant. Each memory node includes both a buried channel portion and a contiguous pinned diode portion having different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion during global charge transfer from an adjacent photodiode. The p-type vertical (potential) barrier implant is coupled to ground, and the bulk substrate is switched between a low integration voltage level during integration periods, and a high reset voltage level, whereby the photodiodes are globally reset without requiring reset transistors. P-type sinker implant sections and p-type vertical barrier implants form box-like diffusions around each pixel's photodiode and memory node.