Global Shutter Pixel Memory Node Built-In Field
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional CMOS image sensors with global shutter (GS) technology face challenges in reducing noise and image distortion due to parasitic charge generation during readout, especially in low-light conditions, and require higher operating voltages that are difficult to support with current CMOS process technologies.
Innovation Solution
The implementation of a CMOS image sensor pixel design featuring a memory node with two contiguous doped regions generating a built-in lateral electric field, which facilitates faster charge transfer from the photodiode to the memory node and then to the floating diffusion, reducing dark current and image distortion, while operating at lower voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional GS pixel arrangement is used to capture image data, then global shutter functionality is achieved, but parasitic charge generation occurs during readout especially in low-light conditions
Solution Approach 1:
The memory node is divided into two separate doped regions: a first doped region for charge storage and a second doped region with higher doping concentration. This segmentation reduces parasitic charge generation by isolating the storage function from the high-doping contact region that causes generation.
Solution Approach 2:
The second doped region is localized with a higher doping concentration specifically at the contact area of the memory node, while the first doped region maintains a lower doping concentration for optimal charge storage. This local quality enhancement reduces parasitic generation at the contact point without affecting the storage region.
2Productivity
If higher operating voltages are used to improve charge transfer, then charge transfer efficiency increases, but compatibility with current CMOS process technologies decreases
Solution Approach 1:
The invention changes the doping concentration parameter of the memory node regions. By using a higher doping concentration in the second doped region, the built-in electric field is enhanced, which improves charge transfer efficiency at lower operating voltages, maintaining compatibility with standard CMOS process technologies.
Solution Approach 2:
The memory node structure generates its own built-in electric field through the doping concentration difference between the first and second doped regions. This self-generated field facilitates charge transfer without requiring elevated external operating voltages, enabling the system to serve itself for efficient charge transfer within standard voltage ranges.
3Adaptability or versatility
If memory node stores captured signals for extended periods, then global shutter readout is enabled, but dark current and image distortion increase
Solution Approach 1:
The memory node is segmented into two doped regions with different doping concentrations. The first region provides charge storage capability while the second high-doping region creates a built-in electric field that actively repels minority carriers, reducing dark current during extended storage periods and minimizing image distortion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances charge transfer efficiency, reduces noise, and minimizes image distortion, achieving superior performance in GS CMOS image sensors using present-day CMOS process technologies without the need for elevated operating voltages.
Implementation Method 1
the memory node generates an intrinsic (built-in) lateral electric field that drives (biases) electrons from the first buried channel portion into the diode portion of the memory node
Implementation Method 2
Each pixel includes a sensing element that is capable of converting a portion of an optical image into an electronic signal
Data Source
AI summary
A global shutter (GS) image sensor pixel includes a pinned photodiode connected to a memory node by a first transfer gate transistor, and a floating diffusion connected to the memory node by a second transfer gate transistor. The memory node includes a buried channel portion disposed under the first transfer gate transistor and a contiguous pinned diode portion disposed between the first and second transfer gate transistors, where the two memory node portions have different doping levels such that an intrinsic lateral electrical field drives electrons from the buried channel portion into the pinned diode portion. The floating diffusion node similarly includes a buried channel portion disposed under the second transfer gate transistor and a contiguous pinned diode portion that generate a second intrinsic lateral electrical field that drives electrons into the pinned diode portion of the floating diffusion. A 6T CMOS pixel is disclosed that facilitates low-noise CDS readout.