Global Shutter Pixels With Shared Isolated Storage Capacitors

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Solution Overview

Problem

The challenge in designing compact image sensors for cellular phones is to maintain larger pixels while minimizing sensor size, as smaller pixels result in reduced charge storage capacity and worse signal-to-noise ratios, and rolling blade shutter pixels fail to capture fast-moving objects effectively.

Innovation Solution

The design incorporates a global shutter architecture where multiple pixels share a single capacitor bank, with deep trench isolation structures to reduce surface area consumption and enable efficient charge storage and readout, allowing for simultaneous integration and readout of images.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of pixels is increased, then the resolution is improved, but the pixel size is reduced resulting in reduced charge storage capacity and worse signal-to-noise ratio

Engineering Contradiction:
ImproveresolutionVSAvoidcharge storage capacity
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

Multiple pixels share a common storage capacitor located in a shared storage capacitor area between pixels, rather than each pixel having its own dedicated capacitor. This merging approach reduces the total area consumed by storage capacitors while maintaining adequate charge storage capacity for each pixel, thereby allowing larger pixel sizes with better signal-to-noise ratios while preserving high resolution.

Inventive Principle:
Principle #5Merging (Combining)

2Quantity of substance

If the pixel size is increased to improve charge storage capacity, then the signal-to-noise ratio is improved, but the sensor area increases making it less compact

Engineering Contradiction:
Improvecharge storage capacityVSAvoidsensor area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

Storage capacitors for multiple pixels are merged into a shared common storage capacitor located in a storage capacitor area that is shared between adjacent pixels. This eliminates redundant capacitor structures and reduces the total sensor area, allowing larger pixels with adequate charge storage capacity while maintaining a compact sensor form factor.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared storage capacitor area serves multiple pixels simultaneously, acting as a universal storage resource for the pixel array. This multi-functional approach allows the same physical space to support charge storage for multiple pixels, reducing overall sensor area while maintaining adequate storage capacity for each pixel.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Area of stationary object

If rolling blade shutter pixels are used to reduce sensor area, then the sensor size is reduced, but the ability to capture fast-moving objects is degraded

Engineering Contradiction:
Improvesensor sizeVSAvoidimage capture accuracy for fast-moving objects
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

All pixels in the array simultaneously complete their integration period and transfer their signals to the shared storage capacitor area before readout begins. This preliminary simultaneous transfer ensures that all pixels capture the same temporal moment, enabling accurate capture of fast-moving objects while maintaining a compact sensor design through the shared capacitor architecture.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10263021B2Global shutter pixels having shared isolated storage capacitors within an isolation structure surrounding the perimeter of a pixel array
Publication Date: 2019.04.16 STMICROELECTRONICS (RES & DEV) LTD
  • US10263021B2 patent drawing
  • US10263021B2 patent drawing
  • US10263021B2 patent drawing

AI summary

Disclosed herein is an electronic device including an integrated circuit substrate, with a pixel array area within the integrated circuit substrate. A first deep trench isolation structure is formed in the integrated circuit substrate about a perimeter of the pixel array area. First, second, third, and fourth pixels are within the pixel array area and spaced apart from one another. A storage capacitor area is within the integrated circuit substrate and interior to the first deep trench isolation structure. A second deep trench isolation structure is formed in the integrated circuit substrate about a perimeter of the storage capacitor area. The second deep trench isolation structure may serve to electrically isolate the storage capacitor area from the first, second, third, and fourth pixels.