Global Shutter Image Sensor Stacked Architecture
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Solution Overview
Problem
Global shutter CMOS image sensors, especially those with High Dynamic Range (HDR) capabilities, face challenges in efficiently storing charge due to the need for additional storage nodes, which consume significant pixel area and increase costs, and struggle with low light level resolution and noise in rapidly changing illumination scenes.
Innovation Solution
The implementation of a stacked integrated circuit architecture where pixel circuitry is distributed across multiple chips, allowing larger charge storage regions and incorporating high and low light level readout circuitry on separate chips to manage charge overflow and storage efficiently, enabling global shutter operation with improved dynamic range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional charge storage nodes are added to each pixel for global shutter operation, then global shutter capability is achieved, but pixel area is significantly consumed and manufacturing cost increases
Solution Approach 1:
The patent moves charge storage functionality from the 2D pixel plane to a 3D stacked architecture. Dual-layer pinned photodiodes provide vertical charge storage capacity without expanding horizontal pixel footprint, enabling global shutter operation while maintaining compact pixel dimensions.
Solution Approach 2:
The patent implements nested charge storage by creating dual-layer pinned photodiodes where one photodiode layer is positioned vertically above another. This nested configuration allows both layers to share the same pixel footprint while providing additional charge storage capacity needed for global shutter operation.
2Adaptability or versatility
If larger charge storage capacity is provided for HDR operations, then dynamic range is improved, but pixel area consumption increases further
Solution Approach 1:
The patent exploits the vertical dimension by stacking photodiode layers at different depths. This vertical arrangement provides increased charge storage capacity for HDR operations without consuming additional horizontal pixel area, as both photodiode layers occupy the same footprint but different vertical positions.
Solution Approach 2:
The dual-layer pinned photodiode structure nests charge storage capacity within the same pixel volume. The first and second photodiode layers are nested vertically, providing cumulative charge storage capacity that enhances dynamic range while maintaining compact pixel dimensions.
3Measurement precision
If more transistors are added per pixel for CDS signal processing, then noise performance is improved, but device complexity increases
Solution Approach 1:
The patent segments signal processing functions across multiple specialized chips rather than concentrating all processing in a single pixel circuit. This segmentation distributes complexity, allowing each chip to be optimized for specific functions while reducing the transistor count required within each individual pixel.
Solution Approach 2:
The patent introduces intermediate charge storage nodes (dual-layer pinned photodiodes) that act as mediators between light capture and signal processing. These intermediaries enable simplified per-pixel circuitry by providing natural charge separation and storage, reducing the need for additional transistors while maintaining noise performance through correlated double sampling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the dynamic range and resolution of image sensors, maintaining high performance across a wide range of illumination levels, including those exceeding 100 dB, with reduced noise and increased aperture efficiency, while minimizing the physical area required for charge storage.
Implementation Method 1
Each pixel includes a photodiode that generates signal charge in response to image light
Data Source
AI summary
A global shutter image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a charge storage region, low light level circuitry and high light level circuitry. During high light level conditions, some charge generated by the photodiode may be diverted to the high light level circuitry and the remainder may be transferred to the low light level circuitry. During low light level conditions, all of the generated charge may be transferred to the low light level circuitry. A light shielding structure may be formed over the charge storage region. The circuit components of each pixel may be divided between first and second chips. By forming the components on separate chips and by implementing high light level circuitry, the size of the charge storage region may be reduced while preserving the high dynamic range and low noise of the image sensor during all illumination conditions.