Global SMI Controller for Multi-Core Error Logging Latency
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Solution Overview
Problem
In multi-processor, multi-core information handling systems, the existing method of logging correctable memory errors using System Management Interrupts (SMIs) causes increased latencies due to the need for each core to save, enter, sync, and exit SMI, suspending processing and leading to inefficiencies.
Innovation Solution
A controller is configured to receive local SMI signals, determine if they trigger a global SMI based on predefined rules, and cause all processors to enter a global system management mode (SMM) to log errors in a shared resource, thereby minimizing unnecessary core interruptions and optimizing error logging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each core enters local SMI to log errors individually, then error logging reliability is improved, but system processing speed deteriorates due to repeated save/exit operations
Solution Approach 1:
The patent merges multiple individual core SMI operations into a single global SMI operation. When any core detects an error, instead of each core independently entering SMI to log the error, the system consolidates these operations by entering a single global SMI that handles logging for all cores simultaneously. This is achieved through the SMI handler receiving error indications from multiple cores and logging them in a unified manner, thereby maintaining reliability while eliminating redundant save/exit cycles.
Solution Approach 2:
The global SMI handler is designed with multi-functionality to serve all processor cores. Instead of having separate logging mechanisms for each core, a universal SMI handler processes error logs from any core that triggers an SMI. This universal handler can manage multiple error conditions and log them appropriately, reducing the need for individual core-specific SMI operations while maintaining comprehensive error logging coverage.
2Reliability
If each core saves state and exits SMI individually, then error logging completeness is improved, but system latency increases due to repeated suspension
Solution Approach 1:
The patent combines multiple individual SMI entry/exit operations into a single global SMI operation. When errors are detected across multiple cores, instead of each core independently saving state, entering SMI, logging, and exiting, the system performs a single save operation followed by a single global log operation. This merging approach ensures that all error indications are captured completely while minimizing the time the system spends in suspended state, as the processor exits SMI only once after all errors are logged.
Solution Approach 2:
The system performs preliminary state saving operations before entering the global SMI handler. By saving the processor state in advance and preparing the error logging structure beforehand, the system minimizes the time spent inside the SMI handler. This preliminary preparation ensures that when the global SMI is entered, the logging operation can proceed efficiently without repeated save/restore cycles, thereby reducing overall latency while maintaining logging completeness.
Data Source
AI summary
In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.